linux-kernel - Re: perf, x86: only do lbr init if bts is available

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Date:	Thu, 24 May 2012 19:18:36 +0200
From:	Peter Zijlstra <peterz@...radead.org>
To:	David Ahern <dsahern@...il.com>
Cc:	Stephane Eranian <eranian@...gle.com>,
	LKML <linux-kernel@...r.kernel.org>,
	Gleb Natapov <gleb@...hat.com>, Avi Kivity <avi@...hat.com>
Subject: Re: perf, x86: only do lbr init if bts is available

On Thu, 2012-05-24 at 10:19 -0600, David Ahern wrote:
> KVM recently added support for a version 2 PMU. When passing -cpu host 
> as the CPU model for the guest we get an abnormal configuration from 
> perf's perspective in that the guest identifies the processor as a 
> Westmere or Nehalem (etc):
> 
> [    0.013998] Performance Events: Westmere events, Intel PMU driver.
> 
> 
> but yet the processor does not have the debug store mechanisms 
> (X86_FEATURE_DTES64 is not set) meaning there is no PEBS or BTS.
> 
> Right now the LBR init functions are run based on processor model which 
> leads to attempts to write to LBR MSRs generating messages like:

Right, as Stephane already noted, LBR is not an CPUID enumerated
feature, hence the only thing you can do is go by model. So if you set
qemu -cpu host but fail to implement all the architectural MSRs that go
with that model you get to keep the pieces.

Not really our problem.
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