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Message-ID: <4FC536A5.6020600@zytor.com>
Date: Tue, 29 May 2012 13:50:45 -0700
From: "H. Peter Anvin" <hpa@...or.com>
To: Yinghai Lu <yinghai@...nel.org>
CC: David Miller <davem@...emloft.net>,
Tony Luck <tony.luck@...el.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Linus Torvalds <torvalds@...ux-foundation.org>,
Steven Newbury <steve@...wbury.org.uk>,
Andrew Morton <akpm@...ux-foundation.org>,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 02/11] PCI: Try to allocate mem64 above 4G at first
On 05/29/2012 01:46 PM, Yinghai Lu wrote:
> On Tue, May 29, 2012 at 12:03 PM, H. Peter Anvin <hpa@...or.com> wrote:
>> On 05/29/2012 11:17 AM, Yinghai Lu wrote:
>>>
>>> pci bridge could support 16bits and 32bits io port.
>>> but we did not record if 32bits is supported.
>>>
>>
>> Okay, so this is the actual problem, no?
>
> their fw could not need kernel help to allocate io ports, or they are
> only use device that support 32bit ioport.
>
That barely parses, never mind makes sense.
>>
>>> so during allocating, could have allocated above 64k address to non
>>> 32bit bridge.
>>>
>>> but x86 is ok, because ioport.end always set to 0xffff.
>>> other arches with IO_SPACE_LIMIT with 0xffffffff or
>>> 0xffffffffffffffffUL may have problem.
>>
>> The latter is nonsense, the PCI-side address space is only 32 bits wide.
>>
> maybe they have unified io include ioport and mem io?
>
The bus-side address space should not be more than 32 bits no matter
what. As Bjorn indicates, you seem to be mixing up bus and cpu
addresses all over the place.
-hpa
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