[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date: Wed, 06 Jun 2012 16:38:44 +0200
From: Peter Zijlstra <a.p.zijlstra@...llo.nl>
To: Stephane Eranian <eranian@...gle.com>
Cc: Andi Kleen <ak@...ux.intel.com>, Andi Kleen <andi@...stfloor.org>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 5/5] perf, x86: Prefer RDPMC over RDMSR for reading
counters
On Wed, 2012-06-06 at 16:33 +0200, Stephane Eranian wrote:
> Yes, his patch did but somehow I don't see this code in tip-x86.
> The thing that I would worry about between rdmsrl() and rdpmc()
> is what happens to the upper bits. rdpmc() returns bits [N-1:0] of
> the N-bit counters. N is 48 (or 40) nowadays. When you read 64 bit
> worth, what do you get in bits [63:N]? are those sign-extended or
> zero-extended. Is that the same behavior across all Intel and AMD
> processors? With perf_events, I think the (N-1)th bit is always set.
>
Queued his patch after I saw Andi's trainwreck -- had totally forgotten
about it :/
For the kernel it doesn't matter, we manually sign-extend for however
many bits the counter has.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists