linux-kernel - Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync

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Message-Id: <AB6D43A9-FC54-40D2-A9B0-8B2E785124F9@kernel.crashing.org>
Date:	Tue, 26 Jun 2012 09:03:42 -0500
From:	Kumar Gala <galak@...nel.crashing.org>
To:	Zhao Chenhui <chenhui.zhao@...escale.com>
Cc:	<linuxppc-dev@...ts.ozlabs.org>, <scottwood@...escale.com>,
	<linux-kernel@...r.kernel.org>, <leoli@...escale.com>
Subject: Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync


On Jun 26, 2012, at 5:25 AM, Zhao Chenhui wrote:

> Do hardware timebase sync. Firstly, stop all timebases, and transfer
> the timebase value of the boot core to the other core. Finally,
> start all timebases.
> 
> Only apply to dual-core chips, such as MPC8572, P2020, etc.
> 
> Signed-off-by: Zhao Chenhui <chenhui.zhao@...escale.com>
> Signed-off-by: Li Yang <leoli@...escale.com>
> ---
> Changes for v6:
> * added 85xx_TB_SYNC
> * added isync() after set_tb()
> * removed extra entries from mpc85xx_smp_guts_ids

Why only on dual-core chips?  Is this because of something related to 2 cores, or related to corenet vs non-corenet SoCs and how turning on/off the timebase works in the SOC?

- k--
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