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Message-ID: <20120627101025.GA10476@localhost.localdomain> Date: Wed, 27 Jun 2012 18:10:25 +0800 From: Zhao Chenhui <chenhui.zhao@...escale.com> To: Kumar Gala <galak@...nel.crashing.org> CC: <linuxppc-dev@...ts.ozlabs.org>, <scottwood@...escale.com>, <linux-kernel@...r.kernel.org>, <leoli@...escale.com> Subject: Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync On Tue, Jun 26, 2012 at 09:03:42AM -0500, Kumar Gala wrote: > > On Jun 26, 2012, at 5:25 AM, Zhao Chenhui wrote: > > > Do hardware timebase sync. Firstly, stop all timebases, and transfer > > the timebase value of the boot core to the other core. Finally, > > start all timebases. > > > > Only apply to dual-core chips, such as MPC8572, P2020, etc. > > > > Signed-off-by: Zhao Chenhui <chenhui.zhao@...escale.com> > > Signed-off-by: Li Yang <leoli@...escale.com> > > --- > > Changes for v6: > > * added 85xx_TB_SYNC > > * added isync() after set_tb() > > * removed extra entries from mpc85xx_smp_guts_ids > > Why only on dual-core chips? Is this because of something related to 2 cores, or related to corenet vs non-corenet SoCs and how turning on/off the timebase works in the SOC? > > - k I am working on a timebase sync patch for corenet SoCs which have more than 2 cores. It is based on this patch. -Chenhui -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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