linux-kernel - [PATCH v10 0/9] X86 TLB flush optimization

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Message-Id: <1340845344-27557-1-git-send-email-alex.shi@intel.com>
Date:	Thu, 28 Jun 2012 09:02:15 +0800
From:	Alex Shi <alex.shi@...el.com>
To:	tglx@...utronix.de, mingo@...hat.com, hpa@...or.com, arnd@...db.de,
	rostedt@...dmis.org, fweisbec@...il.com
Cc:	jeremy@...p.org, alex.shi@...el.com, luto@....edu,
	yinghai@...nel.org, riel@...hat.com, avi@...hat.com,
	len.brown@...el.com, tj@...nel.org, akpm@...ux-foundation.org,
	cl@...two.org, borislav.petkov@....com, ak@...ux.intel.com,
	jbeulich@...e.com, eric.dumazet@...il.com, akinobu.mita@...il.com,
	vapier@...too.org, cpw@....com, steiner@....com,
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	linux-kernel@...r.kernel.org
Subject: [PATCH v10 0/9] X86 TLB flush optimization

Thank for Fengguang's 0-day build system. It found 2 build errors on 
the first and 7th patch.

So this version fix them, introduce a c_detect_tlb() member into
struct cpu_dev for tlb entries detection of specific CPU vendor.

Thanks all of comments and testing on this patchset!

Alex

[PATCH v10 1/9] x86/tlb_info: get last level TLB entry number of CPU
[PATCH v10 2/9] x86/flush_tlb: try flush_tlb_single one by one in
[PATCH v10 3/9] x86/tlb: fall back to flush all when meet a THP
[PATCH v10 4/9] x86/tlb: add tlb_flushall_shift for specific CPU
[PATCH v10 5/9] x86/tlb: add tlb_flushall_shift knob into debugfs
[PATCH v10 6/9] mm/mmu_gather: enable tlb flush range in generic
[PATCH v10 7/9] x86/tlb: enable tlb flush range support for x86
[PATCH v10 8/9] x86/tlb: replace INVALIDATE_TLB_VECTOR by
[PATCH v10 9/9] x86/tlb: do flush_tlb_kernel_range by 'invlpg'
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