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Message-ID: <20120702195855.GH11413@one.firstfloor.org>
Date: Mon, 2 Jul 2012 21:58:55 +0200
From: Andi Kleen <andi@...stfloor.org>
To: Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc: Andi Kleen <andi@...stfloor.org>, x86@...nel.org,
linux-kernel@...r.kernel.org, Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH 1/5] perf, x86: Improve basic Ivy Bridge support v3
On Mon, Jul 02, 2012 at 09:26:34PM +0200, Peter Zijlstra wrote:
> On Mon, 2012-07-02 at 11:43 -0700, Andi Kleen wrote:
> > - As Stephane pointed out .code=0xb1, .umask=0x01 is gone from the
> > event list,
> > so don't do a generic backend stall event on IvyBridge.
>
> 325462-043US, May 2012:
>
> Page 3135, Table 19-2. Non-Architectural Performance Events In the
> Processor Core of Third Generation Intel Core i7, i5, i3 Processors
The table is outdated.
But if you insist can readd it. It's just unlikely to work.
-Andi
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