linux-kernel - Re: [PATCH v4] clk: Add support for rate table based dividers

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Message-ID: <CAJOA=zO27M3YLSpEZRmumRhGHdQQ+Km7_CyP48UtQo6NseTG-w@mail.gmail.com>
Date:	Mon, 2 Jul 2012 16:33:01 -0700
From:	"Turquette, Mike" <mturquette@...com>
To:	Rajendra Nayak <rnayak@...com>
Cc:	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4] clk: Add support for rate table based dividers

On Fri, Jun 29, 2012 at 6:36 AM, Rajendra Nayak <rnayak@...com> wrote:
> Some divider clks do not have any obvious relationship
> between the divider and the value programmed in the
> register. For instance, say a value of 1 could signify divide
> by 6 and a value of 2 could signify divide by 4 etc.
> Also there are dividers where not all values possible
> based on the bitfield width are valid. For instance
> a 3 bit wide bitfield can be used to program a value
> from 0 to 7. However its possible that only 0 to 4
> are valid values.
>
> All these cases need the platform code to pass a simple
> table of divider/value tuple, so the framework knows
> the exact value to be written based on the divider
> calculation and can also do better error checking.
>
> This patch adds support for such rate table based
> dividers and as part of the support adds a new
> registration function 'clk_register_divider_table()'
> and a new macro for static definition
> 'DEFINE_CLK_DIVIDER_TABLE'.
>
> Signed-off-by: Rajendra Nayak <rnayak@...com>

Thanks for updating this one.  I've taken it into clk-next.

Regards,
Mike
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