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Date:	Tue, 3 Jul 2012 16:50:41 +0200
From:	Christoph Egger <Christoph.Egger@....com>
To:	"Luck, Tony" <tony.luck@...el.com>
CC:	Jan Beulich <JBeulich@...e.com>,
	"Liu, Jinsong" <jinsong.liu@...el.com>,
	IanCampbell <Ian.Campbell@...rix.com>,
	"Raj, Ashok" <ashok.raj@...el.com>,
	"Dugger, Donald D" <donald.d.dugger@...el.com>,
	"Shan, Haitao" <haitao.shan@...el.com>,
	"Nakajima, Jun" <jun.nakajima@...el.com>,
	"Li, Susie" <susie.li@...el.com>,
	"Auld, Will" <will.auld@...el.com>,
	"Zhang, Xiantao" <xiantao.zhang@...el.com>,
	"Jiang, Yunhong" <yunhong.jiang@...el.com>,
	"xen-devel@...ts.xensource.com" <xen-devel@...ts.xensource.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	KeirFraser <keir@....org>
Subject: Re: [Xen-devel] [xen vMCE RFC V0.2] xen vMCE design

On 07/03/12 15:26, Luck, Tony wrote:

>> I'm not convinced of the need, and would prefer aiming at a
>> shared implementation unless issues arise that make this
>> impossible.
> 
> It does sound odd. Yes, Intel and AMD have differences around CMCI ... but we are never
> going to send a CMCI to a guest (there is no point, it can't do anything useful with the
> information, it may do something pointlessly stupid like stop using a guest physical page).
> The only reason I suggested making MCG_CAP pretend that CMCI was supported was a
> small optimization ... if a Linux guest sees that CMCI is supported, it will not poll the machine
> check banks looking for corrected errors.


Are you talking about PV or HVM guest?

For HVM guests yes it makes sense to disable CMCI in MCG_CAP for both
AMD and Intel.

PV guests never read MCE MSRs directly. They install a trap handler and
use the hypercall to fetch the error telemetry. The xen interface is
common to both AMD and Intel - it's basically just an array of bytes.
The first bytes tell you how you can cast and interpret the bytes.
That *content* is specific to AMD or Intel.

How much logic can be shared is almost a matter of software design
and not hardware design.

Christoph

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