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Message-Id: <20120712135735.7678a50ffb107e3094af27b8@canb.auug.org.au>
Date: Thu, 12 Jul 2012 13:57:35 +1000
From: Stephen Rothwell <sfr@...b.auug.org.au>
To: Alexander Graf <agraf@...e.de>
Cc: linux-next@...r.kernel.org, linux-kernel@...r.kernel.org,
Bharat Bhushan <r65777@...escale.com>,
Michael Neuling <mikey@...ling.org>,
Benjamin Herrenschmidt <benh@...nel.crashing.org>,
Paul Mackerras <paulus@...ba.org>,
<linuxppc-dev@...ts.ozlabs.org>
Subject: linux-next: manual merge of the kvm-ppc tree with the powerpc tree
Hi Alexander,
Today's linux-next merge of the kvm-ppc tree got a conflict in
arch/powerpc/kvm/booke_interrupts.S between commit c75df6f96c59
("powerpc: Fix usage of register macros getting ready for %r0 change")
from the powerpc tree and commit fc372c0843b8 ("booke: Added crit/mc
exception handler for e500v2") from the kvm-ppc tree.
I fixed it up (see below - could do with checking) and can carry the fix
as necessary.
--
Cheers,
Stephen Rothwell sfr@...b.auug.org.au
diff --cc arch/powerpc/kvm/booke_interrupts.S
index 8fd4b2a,09456c4..0000000
--- a/arch/powerpc/kvm/booke_interrupts.S
+++ b/arch/powerpc/kvm/booke_interrupts.S
@@@ -52,16 -53,21 +52,21 @@@
(1<<BOOKE_INTERRUPT_PROGRAM) | \
(1<<BOOKE_INTERRUPT_DTLB_MISS))
- .macro KVM_HANDLER ivor_nr
+ .macro KVM_HANDLER ivor_nr scratch srr0
_GLOBAL(kvmppc_handler_\ivor_nr)
/* Get pointer to vcpu and record exit number. */
- mtspr SPRN_SPRG_WSCRATCH0, r4
+ mtspr \scratch , r4
mfspr r4, SPRN_SPRG_RVCPU
- stw r3, VCPU_GPR(r3)(r4)
- stw r5, VCPU_GPR(r5)(r4)
- stw r6, VCPU_GPR(r6)(r4)
++ stw r3, VCPU_GPR(R3)(r4)
+ stw r5, VCPU_GPR(R5)(r4)
+ stw r6, VCPU_GPR(R6)(r4)
+ mfspr r3, \scratch
mfctr r5
- lis r6, kvmppc_resume_host@h
- stw r3, VCPU_GPR(r4)(r4)
++ stw r3, VCPU_GPR(R4)(r4)
stw r5, VCPU_CTR(r4)
+ mfspr r3, \srr0
+ lis r6, kvmppc_resume_host@h
+ stw r3, VCPU_PC(r4)
li r5, \ivor_nr
ori r6, r6, kvmppc_resume_host@l
mtctr r6
@@@ -99,12 -104,11 +103,11 @@@ _GLOBAL(kvmppc_handler_len
* r5: KVM exit number
*/
_GLOBAL(kvmppc_resume_host)
- stw r3, VCPU_GPR(R3)(r4)
mfcr r3
stw r3, VCPU_CR(r4)
- stw r7, VCPU_GPR(r7)(r4)
- stw r8, VCPU_GPR(r8)(r4)
- stw r9, VCPU_GPR(r9)(r4)
+ stw r7, VCPU_GPR(R7)(r4)
+ stw r8, VCPU_GPR(R8)(r4)
+ stw r9, VCPU_GPR(R9)(r4)
li r6, 1
slw r6, r6, r5
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