lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20120720121848.GA29183@aftab.osrc.amd.com>
Date:	Fri, 20 Jul 2012 14:18:48 +0200
From:	Borislav Petkov <bp@...64.org>
To:	Tony Luck <tony.luck@...el.com>
Cc:	linux-kernel@...r.kernel.org, Ingo Molnar <mingo@...e.hu>,
	Chen Gong <gong.chen@...ux.intel.com>,
	"Huang, Ying" <ying.huang@...el.com>,
	Hidetoshi Seto <seto.hidetoshi@...fujitsu.com>
Subject: Re: [PATCH 2/2] x86/mce: Add quirk for instruction recovery on Sandy
 Bridge processors

On Thu, Jul 19, 2012 at 11:28:46AM -0700, Tony Luck wrote:
> Sandy Bridge processors follow the SDM (Vol 3B, Table 15-20) and set
> both the RIPV and EIPV bits in the MCG_STATUS register to zero for
> machine checks during instruction fetch. This is more than a little
> counter-intuitive and means that Linux cannot recover from these
> errors. Rather than insert special case code at several places in mce.c
> and mce-severity.c, we pretend the EIPV bit was set for just this case
> early in processing the machine check.
> 
> Signed-off-by: Tony Luck <tony.luck@...el.com>

Looks ok, just minor nitpick below.

> ---
>  arch/x86/kernel/cpu/mcheck/mce.c | 43 +++++++++++++++++++++++++++++++++++++---
>  1 file changed, 40 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
> index da27c5d..e65e738 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce.c
> @@ -102,6 +102,8 @@ DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
>  
>  static DEFINE_PER_CPU(struct work_struct, mce_work);
>  
> +static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
> +
>  /*
>   * CPU/chipset specific EDAC code can register a notifier call here to print
>   * MCE errors in a human-readable form.
> @@ -649,14 +651,18 @@ EXPORT_SYMBOL_GPL(machine_check_poll);
>   * Do a quick check if any of the events requires a panic.
>   * This decides if we keep the events around or clear them.
>   */
> -static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp)
> +static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
> +			  struct pt_regs *regs)
>  {
>  	int i, ret = 0;
>  
>  	for (i = 0; i < banks; i++) {
>  		m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
> -		if (m->status & MCI_STATUS_VAL)
> +		if (m->status & MCI_STATUS_VAL) {
>  			__set_bit(i, validp);
> +			if (quirk_no_way_out)
> +				quirk_no_way_out(i, m, regs);

Maybe define a default empty quirk_no_way_out() on the remaining
families/vendors so that the compiler can optimize it away and we save
ourselves the if-test?

-- 
Regards/Gruss,
Boris.

Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach
GM: Alberto Bozzo
Reg: Dornach, Landkreis Muenchen
HRB Nr. 43632 WEEE Registernr: 129 19551
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ