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Message-ID: <20120814153413.GA18601@localhost>
Date:	Tue, 14 Aug 2012 23:34:13 +0800
From:	Fengguang Wu <fengguang.wu@...el.com>
To:	Andrew Morton <akpm@...ux-foundation.org>
Cc:	"Eric W. Biederman" <ebiederm@...ssion.com>,
	linux-kernel@...r.kernel.org, Mark Salter <msalter@...hat.com>,
	Aurelien Jacquiot <a-jacquiot@...com>,
	linux-c6x-dev@...ux-c6x.org, Lennox Wu <lennox.wu@...il.com>,
	Guan Xuetao <gxt@...c.pku.edu.cn>
Subject: [PATCH] select GENERIC_ATOMIC64 for c6x/score/unicore32 archs

Sorry I have no compilers for build testing these changes, however the
risk looks low and it's much better than to leave the arch broken,
considering that Eric will do atomic64_t in the core fs/namespace.c code.

CC: "Eric W. Biederman" <ebiederm@...ssion.com>
Signed-off-by: Fengguang Wu <fengguang.wu@...el.com>
---

Andrew: the arch maintainers have been CCed. Best is the maintainers
respond, test and perhaps take the corresponding change. Let's see how
this will work out..


 arch/c6x/Kconfig       |    1 +
 arch/score/Kconfig     |    1 +
 arch/unicore32/Kconfig |    1 +
 3 files changed, 3 insertions(+)

--- linux.orig/arch/c6x/Kconfig	2012-06-14 22:29:58.187502107 +0800
+++ linux/arch/c6x/Kconfig	2012-08-14 23:23:18.147838692 +0800
@@ -16,6 +16,7 @@ config C6X
 	select OF
 	select OF_EARLY_FLATTREE
 	select GENERIC_CLOCKEVENTS
+	select GENERIC_ATOMIC64
 
 config MMU
 	def_bool n
--- linux.orig/arch/score/Kconfig	2012-06-14 22:29:58.219502109 +0800
+++ linux/arch/score/Kconfig	2012-08-14 23:23:37.691839156 +0800
@@ -10,6 +10,7 @@ config SCORE
        select ARCH_DISCARD_MEMBLOCK
        select GENERIC_CPU_DEVICES
        select GENERIC_CLOCKEVENTS
+       select GENERIC_ATOMIC64
 
 choice
 	prompt "System type"
--- linux.orig/arch/unicore32/Kconfig	2012-07-25 19:09:37.671358715 +0800
+++ linux/arch/unicore32/Kconfig	2012-08-14 23:23:52.351839505 +0800
@@ -14,6 +14,7 @@ config UNICORE32
 	select GENERIC_IRQ_SHOW
 	select ARCH_WANT_FRAME_POINTERS
 	select GENERIC_IOMAP
+	select GENERIC_ATOMIC64
 	help
 	  UniCore-32 is 32-bit Instruction Set Architecture,
 	  including a series of low-power-consumption RISC chip
--
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