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Message-ID: <20120815092804.GA14676@x1.osrc.amd.com>
Date: Wed, 15 Aug 2012 11:28:04 +0200
From: Borislav Petkov <bp@...en8.de>
To: Jussi Kivilinna <jussi.kivilinna@...et.fi>
Cc: Johannes Goetzfried
<Johannes.Goetzfried@...ormatik.stud.uni-erlangen.de>,
Herbert Xu <herbert@...dor.apana.org.au>,
linux-kernel@...r.kernel.org, linux-crypto@...r.kernel.org,
Tilo Müller
<tilo.mueller@...ormatik.uni-erlangen.de>
Subject: Re: [PATCH] crypto: twofish - add x86_64/avx assembler implementation
On Wed, Aug 15, 2012 at 11:42:16AM +0300, Jussi Kivilinna wrote:
> I started thinking about the performance on AMD Bulldozer.
> vmovq/vmovd/vpextr*/vpinsr* between FPU and general purpose registers
> on AMD CPU is alot slower (latencies from 8 to 12 cycles) than on
> Intel sandy-bridge (where instructions have latency of 1 to 2). See:
> http://www.agner.org/optimize/instruction_tables.pdf
>
> It would be really good, if implementation could be tested on AMD CPU
> to determinate, if it causes performance regression. However I don't
> have access to machine with such CPU.
But I do. :)
And if you tell me exactly how to run the tests and on what kernel, I'll
try to do so.
HTH.
--
Regards/Gruss,
Boris.
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