linux-kernel - Re: [PATCH v2 05/31] arm64: MMU initialisation

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Message-ID: <CAMQu2gxpmCZqAqZ1KCXoxg3vXQLqdFRv+nQ2vt0FeDzpGvNc7A@mail.gmail.com>
Date:	Fri, 17 Aug 2012 15:55:25 +0530
From:	"Shilimkar, Santosh" <santosh.shilimkar@...com>
To:	Catalin Marinas <catalin.marinas@....com>
Cc:	"linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	Will Deacon <Will.Deacon@....com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Arnd Bergmann <arnd@...db.de>
Subject: Re: [PATCH v2 05/31] arm64: MMU initialisation

On Fri, Aug 17, 2012 at 3:45 PM, Catalin Marinas
<catalin.marinas@....com> wrote:
> On Fri, Aug 17, 2012 at 11:06:11AM +0100, Santosh Shilimkar wrote:
>> On Tuesday 14 August 2012 11:22 PM, Catalin Marinas wrote:
>> > This patch contains the initialisation of the memory blocks, MMU
>> > attributes and the memory map. Only five memory types are defined:
>> > Device nGnRnE (equivalent to Strongly Ordered), Device nGnRE (classic
>> > Device memory), Device GRE, Normal Non-cacheable and Normal Cacheable.
>> > Cache policies are supported via the memory attributes register
>> > (MAIR_EL1) and only affect the Normal Cacheable mappings.
>> >
>> > This patch also adds the SPARSEMEM_VMEMMAP initialisation.
>> >
>> > Signed-off-by: Will Deacon<will.deacon@....com>
>> > Signed-off-by: Catalin Marinas<catalin.marinas@....com>
>> > ---
>>
>> Whats the difference between Device nGnRE and Device GRE ?
>> Sorry, I haven't gone through the specs yet and hence the
>> question.
>
> G - gathering (multiple reads/writes into one)
> R - reordering (reads/writes)
> E - early acknowledgement (the write may have not hit the device before
>     the instruction returns).
>
> The 'n' in front just negates the meaning.
>
> So the Device memory as we know it on ARMv7 is equivalent to nGnRE. The
> Strongly Ordered is nGnRnE. GRE is pretty much like Normal Non-cacheable
> memory but with Device mapping, so there are restrictions on unaligned
> accesses.
>
Thanks for explaining it so clearly.

>> > +#ifdef CONFIG_ZONE_DMA32
>> > +   /* 4GB maximum for 32-bit only capable devices */
>> > +   max_dma32 = min(max, MAX_DMA32_PFN);
>> > +   zone_size[ZONE_DMA32] = max_dma32 - min;
>> > +#endif
>>
>> Do you see need of supporting DMA32 on arm64 SOCs ?
>
> I've got some questions from partners but those devices may just be
> hidden behind an iommu. For now I left it in.
>
ok.

>> > +static struct cachepolicy cache_policies[] __initdata = {
>> > +   {
>> > +           .policy         = "uncached",
>> > +           .mair           = 0x44,                 /* inner, outer non-cacheable */
>> > +           .tcr            = TCR_IRGN_NC | TCR_ORGN_NC,
>> > +   }, {
>> > +           .policy         = "writethrough",
>> > +           .mair           = 0xaa,                 /* inner, outer write-through, read-allocate */
>> > +           .tcr            = TCR_IRGN_WT | TCR_ORGN_WT,
>>
>> Is WT supported on arm64?
>> On the recent ARMv7 processors, I think WT wasn't supported.
>
> All of WB, WA, WT are just architectural hints. A CPU implementation may
> or may not ignore them but with Linux we try to follow the architecture
> rather than specific implementations.
>
Agree.

Regards
Santosh
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