linux-kernel - [tip:perf/urgent] perf/x86: Enable Intel Cedarview Atom suppport

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Message-ID: <tip-3ec18cd8b8f8395d0df604c62ab3bc2cf3a966b4@git.kernel.org>
Date:	Tue, 4 Sep 2012 11:52:15 -0700
From:	tip-bot for Stephane Eranian <eranian@...gle.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, eranian@...gle.com, hpa@...or.com,
	mingo@...nel.org, a.p.zijlstra@...llo.nl, tglx@...utronix.de
Subject: [tip:perf/urgent] perf/x86: Enable Intel Cedarview Atom suppport

Commit-ID:  3ec18cd8b8f8395d0df604c62ab3bc2cf3a966b4
Gitweb:     http://git.kernel.org/tip/3ec18cd8b8f8395d0df604c62ab3bc2cf3a966b4
Author:     Stephane Eranian <eranian@...gle.com>
AuthorDate: Mon, 20 Aug 2012 11:24:21 +0200
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Tue, 4 Sep 2012 17:29:23 +0200

perf/x86: Enable Intel Cedarview Atom suppport

This patch enables perf_events support for Intel Cedarview
Atom (model 54) processors. Support includes PEBS and LBR.
Tested on my Atom N2600 netbook.

Signed-off-by: Stephane Eranian <eranian@...gle.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@...llo.nl>
Link: http://lkml.kernel.org/r/20120820092421.GA11284@quad
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/kernel/cpu/perf_event_intel.c     |    1 +
 arch/x86/kernel/cpu/perf_event_intel_lbr.c |    3 ++-
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 7f2739e..0d3d63a 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
 		break;
 
 	case 28: /* Atom */
+	case 54: /* Cedariew */
 		memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
 
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 520b426..da02e9c 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
 	 * to have an operational LBR which can freeze
 	 * on PMU interrupt
 	 */
-	if (boot_cpu_data.x86_mask < 10) {
+	if (boot_cpu_data.x86_model == 28
+	    && boot_cpu_data.x86_mask < 10) {
 		pr_cont("LBR disabled due to erratum");
 		return;
 	}
--
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