linux-kernel - Re: [PATCH v2 20/31] arm64: User access library function

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Message-ID: <20120906083607.GA13975@arm.com>
Date:	Thu, 6 Sep 2012 09:36:07 +0100
From:	Catalin Marinas <catalin.marinas@....com>
To:	Russell King - ARM Linux <linux@....linux.org.uk>
Cc:	Arnd Bergmann <arnd@...db.de>,
	"linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
	Marc Zyngier <Marc.Zyngier@....com>,
	Will Deacon <Will.Deacon@....com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v2 20/31] arm64: User access library function

On Wed, Sep 05, 2012 at 10:05:34PM +0100, Russell King - ARM Linux wrote:
> On Wed, Sep 05, 2012 at 10:01:37PM +0100, Catalin Marinas wrote:
> > There are indeed a few KB gain in code size but that's probably coming
> > from the exception table since otherwise you just replace a bl with
> > ldrt. It depends on what the compiler does as well, the arm code has
> > some carefully chosen registers when calling the __get_user_x function.
> 
> It's more than that - it's not just the ldr but also a zeroing of a
> temporary register to hold the error code should the instruction fault.
> So it's not only the exception tables but also an increase in the
> main path - and that's where you benefit from having it out of line and
> thereby a hotter i-cache.

On 32-bit we have __get_user() inline and get_user() out of line. What
was the history behind this?

> > If you do the access_ok inline and the __get_user_x separately, the size
> > increase is even greater (at least in the arm64 case it can get to over
> > 20KB). I think x86 does the access_ok check out of line.
> 
> Please talk to Will about get_user() and put_user().  Afterwards you
> will definitely want to keep them out of line on 64-bit ARM.

As I said, I already made the change to always inline get_user/put_user
with some penalty in the Image size but it makes the code cleaner. I'm
not entirely convinced of the performance gain/loss especially on ARMv8
cores with physically tagged caches. There is room for optimisation when
I get real silicon.

-- 
Catalin
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