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Message-Id: <20120907132912.dc29219f9ae62b7befbd7401@canb.auug.org.au>
Date:	Fri, 7 Sep 2012 13:29:12 +1000
From:	Stephen Rothwell <sfr@...b.auug.org.au>
To:	Tomi Valkeinen <tomi.valkeinen@...com>
Cc:	linux-next@...r.kernel.org, linux-kernel@...r.kernel.org,
	Archit Taneja <archit@...com>,
	Florian Tobias Schandinat <FlorianSchandinat@....de>
Subject: linux-next: manual merge of the omap_dss2 tree with Linus' tree
Hi Tomi,
Today's linux-next merge of the omap_dss2 tree got a conflict in drivers/video/omap2/dss/sdi.c between commit 35d678664873 ("OMAPDSS: Fix SDI PLL locking") from Linus' tree and commit 889b4fd7eed2 ("OMAPDSS: SDI: Maintain copy of data pairs in driver data") from the omap_dss2 tree.
Just context changes.  I fixed it up (see below) and can carry the fix as
necessary (no action is required).
-- 
Cheers,
Stephen Rothwell                    sfr@...b.auug.org.au
diff --cc drivers/video/omap2/dss/sdi.c
index f43bfe1,3bf1bfe..0000000
--- a/drivers/video/omap2/dss/sdi.c
+++ b/drivers/video/omap2/dss/sdi.c
@@@ -105,21 -107,8 +107,22 @@@ int omapdss_sdi_display_enable(struct o
  
  	sdi_config_lcd_manager(dssdev);
  
 +	/*
 +	 * LCLK and PCLK divisors are located in shadow registers, and we
 +	 * normally write them to DISPC registers when enabling the output.
 +	 * However, SDI uses pck-free as source clock for its PLL, and pck-free
 +	 * is affected by the divisors. And as we need the PLL before enabling
 +	 * the output, we need to write the divisors early.
 +	 *
 +	 * It seems just writing to the DISPC register is enough, and we don't
 +	 * need to care about the shadow register mechanism for pck-free. The
 +	 * exact reason for this is unknown.
 +	 */
 +	dispc_mgr_set_clock_div(dssdev->manager->id,
 +			&sdi.mgr_config.clock_info);
 +
- 	dss_sdi_init(dssdev->phy.sdi.datapairs);
+ 	dss_sdi_init(sdi.datapairs);
+ 
  	r = dss_sdi_enable();
  	if (r)
  		goto err_sdi_enable;
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