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Message-Id: <201209071910.18527.arnd@arndb.de>
Date:	Fri, 7 Sep 2012 19:10:18 +0000
From:	Arnd Bergmann <arnd@...db.de>
To:	Catalin Marinas <catalin.marinas@....com>
Cc:	linux-arch@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 04/31] arm64: MMU definitions

On Friday 07 September 2012, Catalin Marinas wrote:
> 
> The virtual memory layout is described in
> Documentation/arm64/memory.txt. This patch adds the MMU definitions for
> the 4KB and 64KB translation table configurations. The SECTION_SIZE is
> 2MB with 4KB page and 512MB with 64KB page configuration.
> 
> PHYS_OFFSET is calculated at run-time and stored in a variable (no
> run-time code patching at this stage).
> 
> On the current implementation, both user and kernel address spaces are
> 512G (39-bit) each with a maximum of 256G for the RAM linear mapping.
> Linux uses 3 levels of translation tables with the 4K page configuration
> and 2 levels with the 64K configuration. Extending the memory space
> beyond 39-bit with the 4K pages or 42-bit with 64K pages requires an
> additional level of translation tables.
> 
> The SPARSEMEM configuration is global to all AArch64 platforms and
> allows for 1GB sections with SPARSEMEM_VMEMMAP enabled by default.
> 
> Signed-off-by: Will Deacon <will.deacon@....com>
> Signed-off-by: Catalin Marinas <catalin.marinas@....com>
> Acked-by: Tony Lindgren <tony@...mide.com>

Acked-by: Arnd Bergmann <arnd@...db.de>
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