linux-kernel - linux-next: manual merge of the arm-soc tree with the mtd tree

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [day] [month] [year] [list]

Date:	Mon, 17 Sep 2012 18:02:43 +1000
From:	Stephen Rothwell <sfr@...b.auug.org.au>
To:	Olof Johansson <olof@...om.net>, Arnd Bergmann <arnd@...db.de>,
	<linux-arm-kernel@...ts.infradead.org>
Cc:	linux-next@...r.kernel.org, linux-kernel@...r.kernel.org,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Artem Bityutskiy <artem.bityutskiy@...ux.intel.com>,
	David Woodhouse <dwmw2@...radead.org>
Subject: linux-next: manual merge of the arm-soc tree with the mtd tree

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-imx/clk-imx51-imx53.c between commit 75453a08e365 ("ARM:
i.MX5: Add nand oftree support") from the mtd tree and commit
a745f039b901 ("ARM i.MX53: register CAN clocks") from the arm-soc tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

-- 
Cheers,
Stephen Rothwell                    sfr@...b.auug.org.au

diff --cc arch/arm/mach-imx/clk-imx51-imx53.c
index e81f17a,e5165a8..0000000
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@@ -456,7 -461,10 +462,11 @@@ int __init mx53_clocks_init(unsigned lo
  	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
  	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
  	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
 +	clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
+ 	clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
+ 	clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
+ 	clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
+ 	clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
  
  	/* set SDHC root clock to 200MHZ*/
  	clk_set_rate(clk[esdhc_a_podf], 200000000);

Content of type "application/pgp-signature" skipped