linux-kernel - Re: [PATCH 1/1] perf, Add support for Xeon-Phi PMU

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Message-ID: <20120925114225.GF14490@moon>
Date:	Tue, 25 Sep 2012 15:42:25 +0400
From:	Cyrill Gorcunov <gorcunov@...nvz.org>
To:	Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc:	Vince Weaver <vincent.weaver@...ne.edu>,
	linux-kernel@...r.kernel.org, Paul Mackerras <paulus@...ba.org>,
	Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	eranian@...il.com,
	"Meadows, Lawrence F" <lawrence.f.meadows@...el.com>
Subject: Re: [PATCH 1/1] perf, Add support for Xeon-Phi PMU

On Tue, Sep 25, 2012 at 01:32:38PM +0200, Peter Zijlstra wrote:
> On Thu, 2012-09-20 at 13:03 -0400, Vince Weaver wrote:
> > One additional complication:  some of the cache events map to 
> > event "0".  This causes problems because the generic events code
> > assumes "0" means not-available.  I'm not sure the best way to address
> > that problem. 
> 
> For all except P4 we could remap the 0 value to -2, that has all high
> bits set (like the -1) which aren't used by hardware.
> 
> P4 is stuffing two registers in the 64bit config space and actually has
> them all in use I think.. Cyrill?

Yeah, we use almost all 64 bits in config. I tried to describe the bitmaps
in perf_event_p4.h (see Notes on internal configuration of ESCR+CCCR tuples).

Guys, letme re-read this whole mail thread first since I have no clue
what this remapping about ;)
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