linux-kernel - Re: [PATCH 1/1] perf, Add support for Xeon-Phi PMU

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Message-ID: <alpine.DEB.2.02.1209251039350.6296@vincent-weaver-1.um.maine.edu>
Date:	Tue, 25 Sep 2012 10:45:02 -0400 (EDT)
From:	Vince Weaver <vincent.weaver@...ne.edu>
To:	Cyrill Gorcunov <gorcunov@...nvz.org>
cc:	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Vince Weaver <vincent.weaver@...ne.edu>,
	linux-kernel@...r.kernel.org, Paul Mackerras <paulus@...ba.org>,
	Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	eranian@...il.com,
	"Meadows, Lawrence F" <lawrence.f.meadows@...el.com>
Subject: Re: [PATCH 1/1] perf, Add support for Xeon-Phi PMU


On Tue, 25 Sep 2012, Cyrill Gorcunov wrote:

> So guys, if understand all things correctly it's supposed to use some
> -1/-2 as initial @config value for unsupported events, right? Vince,
> may not it be easier to use bit 19 as a flag of valid event and clear
> it when you write to msr, thus we will not have to change "zero is reserved"
> semantics (otoh i'm not sure if it won't become a problem somewhere in
> future with some new cpu :)

Well, we wouldn't want to use a reserved bit.
In theory we could re-use bit 22 (enable) or bit 20 (APIC enable)
because those values should in theory be set elsewhere and could probably
be masked out at an appropriate place.

Is -2 really a valid cache event on Pentium 4?

Though I admit patching all of the various PMU drivers to use -1/-2 rather 
than 0/-1 will be a pain, especially as many of them just default to 0
with no initialization currently. 

Vince Weaver
vincent.weaver@...ne.edu
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