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Date: Fri, 28 Sep 2012 20:12:43 +0000 From: "Karicheri, Muralidharan" <m-karicheri2@...com> To: Linus Walleij <linus.walleij@...aro.org> CC: "mturquette@...aro.org" <mturquette@...aro.org>, "arnd@...db.de" <arnd@...db.de>, "akpm@...ux-foundation.org" <akpm@...ux-foundation.org>, "shawn.guo@...aro.org" <shawn.guo@...aro.org>, "rob.herring@...xeda.com" <rob.herring@...xeda.com>, "viresh.linux@...il.com" <viresh.linux@...il.com>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "Nori, Sekhar" <nsekhar@...com>, "Hilman, Kevin" <khilman@...com>, "linux@....linux.org.uk" <linux@....linux.org.uk>, "davinci-linux-open-source@...ux.davincidsp.com" <davinci-linux-open-source@...ux.davincidsp.com>, "linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>, "linux-keystone@...t.ti.com - Linux developers for Keystone family of devices (May contain non-TIers)" <linux-keystone@...t.ti.com>, "linux-c6x-dev@...ux-c6x.org" <linux-c6x-dev@...ux-c6x.org>, "Chemparathy, Cyril" <cyril@...com> Subject: RE: [linux-keystone] Re: [PATCH 01/13] clk: davinci - add Main PLL clock driver >> -----Original Message----- >> From: Linus Walleij [mailto:linus.walleij@...aro.org] >> Sent: Thursday, September 27, 2012 9:20 AM >> To: Karicheri, Muralidharan >> Cc: mturquette@...aro.org; arnd@...db.de; akpm@...ux-foundation.org; >> shawn.guo@...aro.org; rob.herring@...xeda.com; viresh.linux@...il.com; linux- >> kernel@...r.kernel.org; Nori, Sekhar; Hilman, Kevin; linux@....linux.org.uk; davinci- >> linux-open-source@...ux.davincidsp.com; linux-arm-kernel@...ts.infradead.org; linux- >> keystone@...t.ti.com - Linux developers for Keystone family of devices (May contain non- >> TIers); linux-c6x-dev@...ux-c6x.org; Chemparathy, Cyril >> Subject: [linux-keystone] Re: [PATCH 01/13] clk: davinci - add Main PLL clock driver >> >> On Wed, Sep 26, 2012 at 8:07 PM, Murali Karicheri <m-karicheri2@...com> wrote: >> >> > +struct clk_davinci_pll_data { >> > + /* physical addresses set by platform code */ >> > + u32 phy_pllm; >> > + /* if PLL has a prediv register this should be non zero */ >> > + u32 phy_prediv; >> > + /* if PLL has a postdiv register this should be non zero */ >> > + u32 phy_postdiv; >> > + /* mapped addresses. should be initialized by */ >> > + void __iomem *pllm; >> > + void __iomem *prediv; >> > + void __iomem *postdiv; >> > + u32 pllm_mask; >> > + u32 prediv_mask; >> > + u32 postdiv_mask; >> > + u32 num; >> > + /* framework flags */ >> > + u32 flags; >> > + /* pll flags */ >> > + u32 pll_flags; >> > + /* use this value for prediv */ >> > + u32 fixed_prediv; >> > + /* multiply PLLM by this factor. By default most SOC set this to zero >> > + * that translates to a multiplier of 1 and incrementer of 1. >> > + * To override default, set this factor >> > + */ >> > + u32 pllm_multiplier; >> > +}; >> > + >> >> No, that's not what I meant. >> >> I meant like this: >> >> /** >> * struct clk_davinci_pll_data - struct holding the PLL data >> * phy_pllm: physical addresses set by platform code >> * phy_prediv: ... >> (...) >> */ >> struct clk_davinci_pll_data { >> u32 phy_pllm; >> u32 phy_prediv; >> (...) >> }; >> Ok. Will do in the next revision. Murali Karicheri Software Design Engineer >> Yours, >> Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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