linux-kernel - Re: [PATCH 3/8] sparc64: Eliminate PTE table memory wastage.

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Message-ID: <507482D7.909@tilera.com>
Date:	Tue, 9 Oct 2012 16:02:31 -0400
From:	Chris Metcalf <cmetcalf@...era.com>
To:	David Miller <davem@...emloft.net>
CC:	<aneesh.kumar@...ux.vnet.ibm.com>, <linux-mm@...ck.org>,
	<sparclinux@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-arch@...r.kernel.org>, <akpm@...ux-foundation.org>,
	<aarcange@...hat.com>, <hannes@...xchg.org>
Subject: Re: [PATCH 3/8] sparc64: Eliminate PTE table memory wastage.

On 10/4/2012 2:23 PM, David Miller wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@...ux.vnet.ibm.com>
> Date: Thu, 04 Oct 2012 22:00:48 +0530
> 
>> David Miller <davem@...emloft.net> writes:
>>
>>> We've split up the PTE tables so that they take up half a page instead
>>> of a full page.  This is in order to facilitate transparent huge page
>>> support, which works much better if our PMDs cover 4MB instead of 8MB.
>>>
>>> What we do is have a one-behind cache for PTE table allocations in the
>>> mm struct.
>>>
>>> This logic triggers only on allocations.  For example, we don't try to
>>> keep track of free'd up page table blocks in the style that the s390
>>> port does.
>>
>> I am also implementing a similar change for powerpc. We have a 64K page
>> size, and want to make sure PMD cover 16MB, which is the huge page size
>> supported by the hardware. I was looking at using the s390 logic,
>> considering we have 16 PMDs mapping to same PTE page. Should we look at
>> generalizing the case so that other architectures can start using the
>> same code ?
> 
> I think until we have multiple cases we won't know what's common or not.
> 
> Each arch has different need.  I need to split the page into two pieces
> so my code is simpler, and juse uses page counting to manage alloc/free.
> 
> Whereas s390 uses an bitmask to manage page state, and also reclaims
> pgtable pages into a per-mm list on free.  I decided not to do that
> and to just let the page allocator do the work.
> 
> So I don't think it's appropriate to think about commonization at this
> time, as even the only two cases existing are very non-common :-)

I'll add arch/tile to the list of architectures that would benefit.
We currently allocate PTEs using the page allocator, but by default
we use 64K pages and 16M huge pages, so with 8-byte PTEs that's
just 2K for the page table, so we could fit 32 of them on a page
if we wished.  Instead, for the time being, we just waste the space.

-- 
Chris Metcalf, Tilera Corp.
http://www.tilera.com
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