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Message-Id: <1350602382-12771-8-git-send-email-andi@firstfloor.org>
Date: Thu, 18 Oct 2012 16:19:15 -0700
From: Andi Kleen <andi@...stfloor.org>
To: a.p.zijlstra@...llo.nl
Cc: x86@...nel.org, linux-kernel@...r.kernel.org, acme@...hat.com,
eranian@...gle.com, Andi Kleen <ak@...ux.intel.com>
Subject: [PATCH 07/34] perf, x86: Support PERF_SAMPLE_ADDR on Haswell
From: Andi Kleen <ak@...ux.intel.com>
Haswell supplies the address for every PEBS memory event, so always fill it in
when the user requested it. It will be 0 when not useful (no memory access)
Signed-off-by: Andi Kleen <ak@...ux.intel.com>
---
arch/x86/kernel/cpu/perf_event_intel_ds.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 5d3d6be..8c893ce 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -637,6 +637,10 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
data.raw = &raw;
}
+ if ((event->attr.sample_type & PERF_SAMPLE_ADDR) &&
+ x86_pmu.intel_cap.pebs_format >= 2)
+ data.addr = ((struct pebs_record_v2 *)pebs)->nhm.dla;
+
if (has_branch_stack(event))
data.br_stack = &cpuc->lbr_stack;
--
1.7.7.6
--
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