linux-kernel - Re: [PATCH 05/31] x86/mm: Reduce tlb flushes from ptep_set_access

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Message-ID: <m2pq45qu0s.fsf@firstfloor.org>
Date:	Fri, 26 Oct 2012 05:48:03 -0700
From:	Andi Kleen <andi@...stfloor.org>
To:	Michel Lespinasse <walken@...gle.com>
Cc:	Linus Torvalds <torvalds@...ux-foundation.org>,
	Rik van Riel <riel@...hat.com>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Andrea Arcangeli <aarcange@...hat.com>,
	Mel Gorman <mgorman@...e.de>,
	Johannes Weiner <hannes@...xchg.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Andrew Morton <akpm@...ux-foundation.org>,
	linux-kernel@...r.kernel.org, linux-mm@...ck.org,
	Ingo Molnar <mingo@...nel.org>
Subject: Re: [PATCH 05/31] x86/mm: Reduce tlb flushes from ptep_set_access_flags()

Michel Lespinasse <walken@...gle.com> writes:

> On Thu, Oct 25, 2012 at 9:23 PM, Linus Torvalds
> <torvalds@...ux-foundation.org> wrote:
>> On Thu, Oct 25, 2012 at 8:57 PM, Rik van Riel <riel@...hat.com> wrote:
>>>
>>> That may not even be needed.  Apparently Intel chips
>>> automatically flush an entry from the TLB when it
>>> causes a page fault.  I assume AMD chips do the same,
>>> because flush_tlb_fix_spurious_fault evaluates to
>>> nothing on x86.
>>
>> Yes. It's not architected as far as I know, though. But I agree, it's
>> possible - even likely - we could avoid TLB flushing entirely on x86.
>
> Actually, it is architected on x86. This was first described in the
> intel appnote 317080 "TLBs, Paging-Structure Caches, and Their
> Invalidation", last paragraph of section 5.1. Nowadays, the same
> contents are buried somewhere in Volume 3 of the architecture manual
> (in my copy: 4.10.4.1 Operations that Invalidate TLBs and
> Paging-Structure Caches)

This unfortunately would only work for processes with no threads
because it only works on the current logical CPU.

-Andi
-- 
ak@...ux.intel.com -- Speaking for myself only
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