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Message-ID: <20121029194203.GK2266@tassilo.jf.intel.com>
Date:	Mon, 29 Oct 2012 12:42:03 -0700
From:	Andi Kleen <ak@...ux.intel.com>
To:	Stephane Eranian <eranian@...gle.com>
Cc:	linux-kernel@...r.kernel.org, peterz@...radead.org, mingo@...e.hu,
	acme@...hat.com, jolsa@...hat.com, ming.m.lin@...el.com
Subject: Re: [Patch v1 04/10] perf/x86: add memory profiling via PEBS Load
 Latency

> +
> +struct attribute *nhm_events_attrs[] = {
> +	EVENT_PTR(CPU_CYCLES),
> +	EVENT_PTR(INSTRUCTIONS),
> +	EVENT_PTR(CACHE_REFERENCES),
> +	EVENT_PTR(CACHE_MISSES),
> +	EVENT_PTR(BRANCH_INSTRUCTIONS),
> +	EVENT_PTR(BRANCH_MISSES),
> +	EVENT_PTR(BUS_CYCLES),
> +	EVENT_PTR(STALLED_CYCLES_FRONTEND),
> +	EVENT_PTR(STALLED_CYCLES_BACKEND),
> +	EVENT_PTR(REF_CPU_CYCLES),
> +	EVENT_PTR(mem_ld_nhm),
> +	NULL,
> +};

I thought Jiri's patch already exports all the generic ones?

Why do you need to replace the whole table?

BTW I still think my approach in the v4 Haswell patchkit 
is simpler and didn't rely on hardcoding these events.

-Andi
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