linux-kernel - Re: [PATCH] Set bit 22 in the PL310 (cache controller) AuxCtlr register

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Message-ID: <20121112064547.GN32313@localhost.localdomain>
Date:	Mon, 12 Nov 2012 12:15:47 +0530
From:	Shiraz Hashim <shiraz.hashim@...com>
To:	Will Deacon <will.deacon@....com>
Cc:	Russell King <linux@....linux.org.uk>,
	"spear-devel@...t.st.com" <spear-devel@...t.st.com>,
	"alain.pasteur@...com" <alain.pasteur@...com>,
	"Joerg.Wienand@....de" <Joerg.Wienand@....de>, <amit.goel@...com>,
	Catalin Marinas <Catalin.Marinas@....com>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] Set bit 22 in the PL310 (cache controller) AuxCtlr
 register

On Fri, Nov 09, 2012 at 09:54:01AM +0000, Will Deacon wrote:
> On Fri, Nov 09, 2012 at 04:01:52AM +0000, Shiraz Hashim wrote:
> > From: Catalin Marinas <catalin.marinas@....com>
> > 
> > Clearing bit 22 in the PL310 Auxiliary Control register (shared
> > attribute override enable) has the side effect of transforming Normal
> > Shared Non-cacheable reads into Cacheable no-allocate reads.
> > 
> > Coherent DMA buffers in Linux always have a Cacheable alias via the
> > kernel linear mapping and the processor can speculatively load cache
> > lines into the PL310 controller. With bit 22 cleared, Non-cacheable
> > reads would unexpectedly hit such cache lines leading to buffer
> > corruption.
> 
> Is this still the case with recent kernels? I thought the dma-mapping/cma
> work avoided the cacheable alias, but perhaps I'm mistaken.

I haven't used CMA but DMA mappings are still normal memory
non-cacheable.

--
regards
Shiraz
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