linux-kernel - Re: [PATCH] x86/Sandy Bridge: reserve pages when integrated graphics is present

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Date:	Wed, 14 Nov 2012 23:24:43 +0000
From:	Alan Cox <alan@...rguk.ukuu.org.uk>
To:	Jesse Barnes <jbarnes@...tuousgeek.org>
Cc:	intel-gfx@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] x86/Sandy Bridge: reserve pages when integrated
 graphics is present

On Wed, 14 Nov 2012 13:55:34 -0800
Jesse Barnes <jbarnes@...tuousgeek.org> wrote:

> On Wed, 14 Nov 2012 21:19:05 +0000
> Alan Cox <alan@...rguk.ukuu.org.uk> wrote:
> 
> > On Wed, 14 Nov 2012 20:43:31 +0000
> > Jesse Barnes <jbarnes@...tuousgeek.org> wrote:
> > 
> > > SNB graphics devices have a bug that prevent them from accessing certain
> > > memory ranges, namely anything below 1M and in the pages listed in the
> > > table.  So reserve those at boot if set detect a SNB gfx device on the
> > > CPU to avoid GPU hangs.
> > 
> > What happens if the other addresses map to an external memory object - eg
> > a PCI device which is a legitimate DMA source for video overlay etc ?
> 
> Other addresses as in the 5 pages high in the address space?  I'm not
> sure how to do what I want with memblock, doesn't it just allocate RAM
> not I/O space?... /me looks at the memblock API
> 
> Or do you mean if we map GTT pages to point at some non-RAM region will
> SNB gfx be able to decode them?  If that's the question, then I think
> the answer is no, but I don't have enough detail on the hw bug to be
> certain.
> 
> > I assume this is just for GPU fetches from main memory ?
> 
> AIUI, it's an address decoder bug, so it would affect any fetch by the
> GPU through its memory interface glue.

Well the extreme case (and I suspect one we don't care about too much in
reality) is a box with a PCI/E or similar MMIO graphics device which is
taking part in Dave Airlie's wonderous new graphics architecture so being
rendered into or fetched by the Intel GPU and whose PCI/E space is mapped
crossing one of those addresses.

The other case of concern would be if the Intel IOMMU had mappings there
that were then touched in some way by the GPU ?

Alan
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