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Message-ID: <1353390792.3833.1.camel@rzhang1-mobl4>
Date: Tue, 20 Nov 2012 13:53:12 +0800
From: Zhang Rui <rui.zhang@...el.com>
To: Kyungmin Park <kmpark@...radead.org>
Cc: Jonghwan Choi <jhbird.choi@...sung.com>,
"jonghwa3.lee" <jonghwa3.lee@...sung.com>,
open list <linux-kernel@...r.kernel.org>,
Amit Daniel Kachhap <amit.kachhap@...aro.org>,
Sachin Kamat <sachin.kamat@...aro.org>,
Linux PM list <linux-pm@...r.kernel.org>,
dg77.kim@...sung.com
Subject: Re: [PATCH v3 1/2] thermal: exynos: Fix wrong bit to control tmu
core
On Tue, 2012-11-20 at 10:39 +0900, Kyungmin Park wrote:
> On 11/20/12, Jonghwan Choi <jhbird.choi@...sung.com> wrote:
> > [0]bit is used to enable/disable tmu core. [1] bit is a reserved bit.
> >
> > Signed-off-by: Jonghwan Choi <jhbird.choi@...sung.com>
> Acked-by: Kyungmin Park <kyungmin.park@...sung.com>
Amit and Donggeun Kim,
any comments on this patch?
thanks,
rui
> > ---
> > drivers/thermal/exynos_thermal.c | 16 ++++++++++++----
> > 1 files changed, 12 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/thermal/exynos_thermal.c
> > b/drivers/thermal/exynos_thermal.c
> > index 6dd29e4..129e827 100644
> > --- a/drivers/thermal/exynos_thermal.c
> > +++ b/drivers/thermal/exynos_thermal.c
> > @@ -52,9 +52,12 @@
> >
> > #define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
> > #define EXYNOS_TMU_GAIN_SHIFT 8
> > +#define EXYNOS_TMU_GAIN_MASK (0xF << EXYNOS_TMU_GAIN_SHIFT)
> > #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
> > -#define EXYNOS_TMU_CORE_ON 3
> > -#define EXYNOS_TMU_CORE_OFF 2
> > +#define EXYNOS_TMU_REF_VOLTAGE_MASK (0x1F <<
> > EXYNOS_TMU_REF_VOLTAGE_SHIFT)
> > +#define EXYNOS_TMU_CORE_ON BIT(0)
> > +#define EXYNOS_TMU_CORE_ON_SHIFT 0
> > +#define EXYNOS_TMU_CORE_ON_MASK (0x1 <<
> > EXYNOS_TMU_CORE_ON_SHIFT)
> > #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50
> >
> > /* Exynos4210 specific registers */
> > @@ -85,7 +88,9 @@
> > #define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 16)
> > #define EXYNOS_MUX_ADDR_VALUE 6
> > #define EXYNOS_MUX_ADDR_SHIFT 20
> > +#define EXYNOS_MUX_ADDR_MASK (0x7 << EXYNOS_MUX_ADDR_SHIFT)
> > #define EXYNOS_TMU_TRIP_MODE_SHIFT 13
> > +#define EXYNOS_TMU_TRIP_MODE_MASK (0x7 << EXYNOS_TMU_TRIP_MODE_SHIFT)
> >
> > #define EFUSE_MIN_VALUE 40
> > #define EFUSE_MAX_VALUE 100
> > @@ -650,10 +655,14 @@ static void exynos_tmu_control(struct platform_device
> > *pdev, bool on)
> > mutex_lock(&data->lock);
> > clk_enable(data->clk);
> >
> > - con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
> > + con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
> > + con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK | EXYNOS_TMU_GAIN_MASK |
> > + EXYNOS_TMU_CORE_ON_MASK);
> > + con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
> > pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
> >
> > if (data->soc == SOC_ARCH_EXYNOS) {
> > + con &= ~(EXYNOS_TMU_TRIP_MODE_MASK | EXYNOS_MUX_ADDR_MASK);
> > con |= pdata->noise_cancel_mode <<
> > EXYNOS_TMU_TRIP_MODE_SHIFT;
> > con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
> > }
> > @@ -665,7 +674,6 @@ static void exynos_tmu_control(struct platform_device
> > *pdev, bool on)
> > pdata->trigger_level1_en << 4 |
> > pdata->trigger_level0_en;
> > } else {
> > - con |= EXYNOS_TMU_CORE_OFF;
> > interrupt_en = 0; /* Disable all interrupts */
> > }
> > writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
> > --
> > 1.7.4.1
> >
> > --
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