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Message-Id: <1354833773-22845-3-git-send-email-mark.langsdorf@calxeda.com> Date: Thu, 6 Dec 2012 16:42:49 -0600 From: Mark Langsdorf <mark.langsdorf@...xeda.com> To: linux-kernel@...r.kernel.org, cpufreq@...r.kernel.org, linux-pm@...r.kernel.org, linux-arm-kernel@...ts.infradead.org Cc: Mark Langsdorf <mark.langsdorf@...xeda.com>, Rob Herring <rob.herring@...xeda.com> Subject: [PATCH 2/6 v9] clk, highbank: Prevent glitches in non-bypass reset mode The highbank clock will glitch with the current code if the clock rate is reset without relocking the PLL. Program the PLL correctly to prevent glitches. Signed-off-by: Mark Langsdorf <mark.langsdorf@...xeda.com> Signed-off-by: Rob Herring <rob.herring@...xeda.com> Acked-by: Mike Turquette <mturquette@...aro.org> --- Changes from v6, v7, v8 None. Changes from v5 Added Mike Turquette's ack. Changes from v4 None. Changes from v3 Changelog text and patch name now correspond to the actual patch. was clk, highbank: remove non-bypass reset mode. Changes from v2 None. Changes from v1 Removed erroneous reformating. drivers/clk/clk-highbank.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c index 52fecad..3a0b723 100644 --- a/drivers/clk/clk-highbank.c +++ b/drivers/clk/clk-highbank.c @@ -182,8 +182,10 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate, reg |= HB_PLL_EXT_ENA; reg &= ~HB_PLL_EXT_BYPASS; } else { + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); reg &= ~HB_PLL_DIVQ_MASK; reg |= divq << HB_PLL_DIVQ_SHIFT; + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); } writel(reg, hbclk->reg); -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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