linux-kernel - [PATCH] x86, perf, bts: disable BTS from Nehalem to Ivy Bridge

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-Id: <1354876511-25294-1-git-send-email-markus.t.metzger@intel.com>
Date:	Fri,  7 Dec 2012 11:35:11 +0100
From:	markus.t.metzger@...el.com
To:	mingo@...hat.com, mingo@...e.hu
Cc:	markus.t.metzger@...el.com, linux-kernel@...r.kernel.org,
	Mark Kettenis <kettenis@....org>,
	Pedro Alves <palves@...hat.com>,
	Jan Kratochvil <jan.kratochvil@...hat.com>,
	gdb-patches@...rceware.org
Subject: [PATCH] x86, perf, bts: disable BTS from Nehalem to Ivy Bridge

From: Markus Metzger <markus.t.metzger@...el.com>

Starting with Nehalem, the BTS "from" information may in some cases be
incorrect (AAJ122).

This has been detected while adding branch tracing support to gdb, where it
results in sporadic test fails.

Disable BTS support on Nehalem, Westmere, Sandy Bridge, and Ivy Bridge.

CC: Mark Kettenis <kettenis@....org>
CC: Pedro Alves <palves@...hat.com>
CC: Jan Kratochvil <jan.kratochvil@...hat.com>
CC: gdb-patches@...rceware.org
Signed-off-by: Markus Metzger <markus.t.metzger@...el.com>
---
 arch/x86/kernel/cpu/perf_event_intel.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 6bca492..e72aac9 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1893,6 +1893,16 @@ static __init void intel_nehalem_quirk(void)
 	}
 }
 
+static __init void intel_disable_bts(void)
+{
+	/*
+	 * Erratum AAJ122: LBR, BTM, or BTS records may have incorrect branch
+	 * "from" information afer an EIST transition, T-states, C1E, or
+	 * Adaptive Thermal Throttling.
+	 */
+	x86_pmu.bts = 0;
+}
+
 __init int intel_pmu_init(void)
 {
 	union cpuid10_edx edx;
@@ -2003,6 +2013,7 @@ __init int intel_pmu_init(void)
 			X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
 
 		x86_add_quirk(intel_nehalem_quirk);
+		intel_disable_bts();
 
 		pr_cont("Nehalem events, ");
 		break;
@@ -2042,6 +2053,7 @@ __init int intel_pmu_init(void)
 		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
 			X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
 
+		intel_disable_bts();
 		pr_cont("Westmere events, ");
 		break;
 
@@ -2070,6 +2082,7 @@ __init int intel_pmu_init(void)
 		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
 			X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
 
+		intel_disable_bts();
 		pr_cont("SandyBridge events, ");
 		break;
 	case 58: /* IvyBridge */
@@ -2092,6 +2105,7 @@ __init int intel_pmu_init(void)
 		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
 			X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
 
+		intel_disable_bts();
 		pr_cont("IvyBridge events, ");
 		break;
 
-- 
1.7.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/