linux-kernel - Re: [PATCH V4 0/6] perf, amd: Enable AMD family 15h northbridge counters

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Message-ID: <20121210185100.GA31713@jshin-Toonie>
Date:	Mon, 10 Dec 2012 12:51:00 -0600
From:	Jacob Shin <jacob.shin@....com>
To:	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Paul Mackerras <paulus@...ba.org>,
	Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>
CC:	Thomas Gleixner <tglx@...utronix.de>,
	"H. Peter Anvin" <hpa@...or.com>,
	Stephane Eranian <eranian@...gle.com>,
	Robert Richter <rric@...nel.org>, <x86@...nel.org>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V4 0/6] perf, amd: Enable AMD family 15h northbridge
 counters

On Wed, Dec 05, 2012 at 05:04:12PM -0600, Jacob Shin wrote:
> The following patchset enables 4 additional performance counters in
> AMD family 15h processors that count northbridge events -- such as
> number of DRAM accesses.
> 
> This patchset is based on previous work done by Robert Richter
> <rric@...nel.org> :
> 
> https://lkml.org/lkml/2012/6/19/324
> 
> The main differences are:
> 
> * The northbridge counters are indexed contiguously right above the
>   core performance counters.
> 
> * MSR address offset calculations are moved to architecture specific
>   files.
> 
> * Interrups are set up to be delivered only to a single core.
> 
> V4:
> * Moved interrupt core select set up back to event constraints
>   function, sicne during ->hw_config time we do not yet know on which
>   CPU the the event will run on.
> * Tested on and made minor revisions to make sure that the patchset is
>   compatible with upcoming AMD Family 16h processors, and will support
>   core and NB counters without any further patches.
> 
> V3:
> Addressed the following feedback/comments from Robert's review
> * https://lkml.org/lkml/2012/11/16/484
> * https://lkml.org/lkml/2012/11/26/162
> 
> V2:
> Separate out Robert's patches, and add properly ordered certificate of
> origins.
> 
> Jacob Shin (4):
>   perf, amd: Use proper naming scheme for AMD bit field definitions
>   perf, x86: Move MSR address offset calculation to architecture
>     specific files
>   perf, x86: Allow for architecture specific RDPMC indexes
>   perf, amd: Enable northbridge performance counters on AMD family 15h
> 
> Robert Richter (2):
>   perf, amd: Rework northbridge event constraints handler
>   perf, amd: Generalize northbridge constraints code for family 15h
> 
>  arch/x86/include/asm/cpufeature.h    |    2 +
>  arch/x86/include/asm/msr-index.h     |    2 +
>  arch/x86/include/asm/perf_event.h    |   13 +-
>  arch/x86/kernel/cpu/perf_event.c     |    2 +-
>  arch/x86/kernel/cpu/perf_event.h     |   25 ++-
>  arch/x86/kernel/cpu/perf_event_amd.c |  318 ++++++++++++++++++++++++++--------
>  6 files changed, 268 insertions(+), 94 deletions(-)
> 
> -- 

Ping .. ? any comments/feedback ? If things look okay, could you
please commit to tip perf/core ?

Thank you,

-Jacob

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