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Message-ID: <1355493232-21821-1-git-send-email-Varun.Sethi@freescale.com>
Date: Fri, 14 Dec 2012 19:23:52 +0530
From: Varun Sethi <Varun.Sethi@...escale.com>
To: <joerg.roedel@....com>, <iommu@...ts.linux-foundation.org>,
<linuxppc-dev@...ts.ozlabs.org>, <linux-kernel@...r.kernel.org>,
<timur@...escale.com>, <scottwood@...escale.com>
CC: Varun Sethi <Varun.Sethi@...escale.com>
Subject: [PATCH 2/4] iommu/fsl: Add PAMU bypass enable register to ccsr_guts structure.
PAMU bypass enable register added to the ccsr_guts structure.
(This patch has already been applied by Kumar Gala in the linuxppc tree next branch)
Signed-off-by: Timur Tabi <timur@...escale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@...escale.com>
---
arch/powerpc/include/asm/fsl_guts.h | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
index dd5ba2c..77ced0b 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -71,7 +71,9 @@ struct ccsr_guts {
u8 res0c4[0x224 - 0xc4];
__be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
__be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
- u8 res22c[0x800 - 0x22c];
+ u8 res22c[0x604 - 0x22c];
+ __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
+ u8 res608[0x800 - 0x608];
__be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
u8 res804[0x900 - 0x804];
__be32 ircr; /* 0x.0900 - Infrared Control Register */
--
1.7.4.1
--
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