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Message-ID: <CAE9FiQVMkAF8Qk6h3QtKam5jahfS3HE01R4fynyXR-spknJkBA@mail.gmail.com>
Date:	Fri, 14 Dec 2012 12:14:39 -0800
From:	Yinghai Lu <yinghai@...nel.org>
To:	"H. Peter Anvin" <hpa@...or.com>
Cc:	Borislav Petkov <bp@...en8.de>,
	"Yu, Fenghua" <fenghua.yu@...el.com>,
	"mingo@...nel.org" <mingo@...nel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"tglx@...utronix.de" <tglx@...utronix.de>,
	"hpa@...ux.intel.com" <hpa@...ux.intel.com>,
	"linux-tip-commits@...r.kernel.org" 
	<linux-tip-commits@...r.kernel.org>,
	Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>,
	Stefano Stabellini <Stefano.Stabellini@...citrix.com>
Subject: Re: [tip:x86/microcode] x86/microcode_intel_early.c: Early update
 ucode on Intel's CPU

On Fri, Dec 14, 2012 at 12:08 PM, Yinghai Lu <yinghai@...nel.org> wrote:
> On Fri, Dec 14, 2012 at 12:04 PM, Yinghai Lu <yinghai@...nel.org> wrote:
>> On Fri, Dec 14, 2012 at 11:46 AM, H. Peter Anvin <hpa@...or.com> wrote:
>>>
>>> I suspect we don't need init_level4_pgt at all and should just plan to
>>> get rid of it.  Is there any reason we can't just build the proper
>>> kernel page table set in pagetable_init() and switch to it there?
>>
>> then how to pass the info to AP?
>
> also we should merge early_level4_pgt with init_level4_pgt.
>
> and #PE handler could just extend to use BRK ...
>
> but need to make sure BRK get mapped at first, and BRK could cross the
> 1G, 512G boundary ...
>
> that could make things less impact to all.

your current switchover setup in arch/x86/kernel/head_64.S could
handle above 512g and cross boundary?
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