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Date:	Wed, 19 Dec 2012 10:18:39 -0800
From:	Soren Brinkmann <soren.brinkmann@...inx.com>
To:	Michal Simek <michal.simek@...inx.com>, <monstr@...str.eu>
CC:	<linux-kernel@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	John Linn <john.linn@...inx.com>,
	Arnd Bergmann <arnd@...db.de>, <git@...inx.com>,
	<nbowler@...iptictech.com>, <josh.cartwright@...com>,
	Soren Brinkmann <soren.brinkmann@...inx.com>
Subject: [PATCH v2 4/7] arm: zynq: timer: Align columns

Aligning the columns in a block of #defines, so that the values
are starting in the same colum on every line.

Signed-off-by: Soren Brinkmann <soren.brinkmann@...inx.com>
Reviewed-by: Josh Cartwright <josh.cartwright@...com>
---
 arch/arm/mach-zynq/timer.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index 80bf474..4b81ae1 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -35,9 +35,9 @@
  * Timer Register Offset Definitions of Timer 1, Increment base address by 4
  * and use same offsets for Timer 2
  */
-#define XTTCPS_CLK_CNTRL_OFFSET	0x00 /* Clock Control Reg, RW */
-#define XTTCPS_CNT_CNTRL_OFFSET	0x0C /* Counter Control Reg, RW */
-#define XTTCPS_COUNT_VAL_OFFSET	0x18 /* Counter Value Reg, RO */
+#define XTTCPS_CLK_CNTRL_OFFSET		0x00 /* Clock Control Reg, RW */
+#define XTTCPS_CNT_CNTRL_OFFSET		0x0C /* Counter Control Reg, RW */
+#define XTTCPS_COUNT_VAL_OFFSET		0x18 /* Counter Value Reg, RO */
 #define XTTCPS_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
 #define XTTCPS_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
 #define XTTCPS_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */
-- 
1.8.0.2


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