| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <2a6829e8-3578-4fcf-b6d2-406576187abb@VA3EHSMHS004.ehs.local> Date: Wed, 19 Dec 2012 10:18:42 -0800 From: Soren Brinkmann <soren.brinkmann@...inx.com> To: Michal Simek <michal.simek@...inx.com>, <monstr@...str.eu> CC: <linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, John Linn <john.linn@...inx.com>, Arnd Bergmann <arnd@...db.de>, <git@...inx.com>, <nbowler@...iptictech.com>, <josh.cartwright@...com>, Soren Brinkmann <soren.brinkmann@...inx.com> Subject: [PATCH v2 7/7] arm: zynq: timer: Set clock_event cpumask The timers are common to both A9 cores, so let's set the clock event struct's cpumask accordingly, to all possible CPUs. Signed-off-by: Soren Brinkmann <soren.brinkmann@...inx.com> Reviewed-by: Josh Cartwright <josh.cartwright@...com> --- arch/arm/mach-zynq/timer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index 7b2e047..f9fbc9c 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -267,6 +267,7 @@ static void __init zynq_ttc_setup_clockevent(struct device_node *np, ttcce->ce.set_mode = xttcps_set_mode; ttcce->ce.rating = 200; ttcce->ce.irq = irq; + ttcce->ce.cpumask = cpu_possible_mask; __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET); __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, -- 1.8.0.2 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists