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Message-ID: <50D24B27.5080705@zytor.com>
Date: Wed, 19 Dec 2012 15:17:59 -0800
From: "H. Peter Anvin" <hpa@...or.com>
To: Borislav Petkov <bp@...en8.de>, Jacob Shin <jacob.shin@....com>,
Yinghai Lu <yinghai@...nel.org>,
"H. Peter Anvin" <hpa@...ux.intel.com>,
"Yu, Fenghua" <fenghua.yu@...el.com>,
"mingo@...nel.org" <mingo@...nel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"linux-tip-commits@...r.kernel.org"
<linux-tip-commits@...r.kernel.org>,
Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>,
Stefano Stabellini <Stefano.Stabellini@...citrix.com>
Subject: Re: [tip:x86/microcode] x86/microcode_intel_early.c: Early update
ucode on Intel's CPU
On 12/19/2012 03:00 PM, Borislav Petkov wrote:
> On Wed, Dec 19, 2012 at 04:55:06PM -0600, Jacob Shin wrote:
>> Well, really the problem is with any memory hole above 4GB that is too
>> big to be covered by variable range MTRRs as UC.
>
> Why, their PhysBase field is the 40 MSB bits of the physical address.
> That should be more than TB.
>
I presume with "too big" he really means "oddly shaped".
-hpa
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