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Message-ID: <20121221221712.GB22404@pratikp-linux.qualcomm.com> Date: Fri, 21 Dec 2012 14:17:12 -0800 From: Pratik Patel <pratikp@...eaurora.org> To: Russell King - ARM Linux <linux@....linux.org.uk> Cc: Jon Hunter <jon-hunter@...com>, linux-arm-msm@...r.kernel.org, "linus.walleij@...aro.org" <linus.walleij@...aro.org>, Will Deacon <will.deacon@....com>, linux-kernel@...r.kernel.org, "magnus.p.persson@...ricsson.com" <magnus.p.persson@...ricsson.com>, "david.rusling@...aro.org" <david.rusling@...aro.org>, "arve@...roid.com" <arve@...roid.com>, "dsaxena@...aro.org" <dsaxena@...aro.org>, "john.stultz@...aro.org" <john.stultz@...aro.org>, "d-deao@...com" <d-deao@...com>, "christian.bejram@...ricsson.com" <christian.bejram@...ricsson.com>, "devicetree-discuss@...ts.ozlabs.org" <devicetree-discuss@...ts.ozlabs.org>, "linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org> Subject: Re: CoreSight framework and drivers On Thu, Dec 20, 2012 at 11:40:11PM +0000, Russell King - ARM Linux wrote: > On Thu, Dec 20, 2012 at 04:54:38PM -0600, Jon Hunter wrote: > > On 12/20/2012 01:51 PM, Pratik Patel wrote: > > > Ok, so are you referring to making CoreSight devices register > > > with AMBA bus instead of platform bus keeping everything else > > > intact? > > > > Yes exactly. However, please note I am not saying that we should do > > this, and I asking what direction does the community want us to take > > here? Platform bus or AMBA bus? > > One of the issues which worries me about mixing peripheral drivers on > random different buses is... what happens when we end up with a SoC > which gates the APB clock at bus level (there are SoCs which gate the > APB clock at peripheral level.) In other words, an APB bus only gets > clocked upon request. > > We can deal with that with the infrastructure we have in place in the > AMBA bus layer, but not with the platform bus - we'd have to teach the > platform bus driver about the special APB clock instead of having it > handled primerily at the bus layer. > > At least the coresight ETM peripherals make use of the APB bus. They > have a whole pile of registers on the APB bus, and they have the > primecell IDs stored in the last words of the peripheral, again just > like the other primecell devices we have using the AMBA bus layer. > > What I'd say is... why stick it on a different bus type from the other > peripherals which might make things harder in the future? Thanks for the info. I will look into using the AMBA bus instead of the platform bus but one issue I notice is that AMBA framework seems to support one contiguous register space. CoreSight STM typically has a config register space and a stimulus port/channel register space and these can be non-contiguous in the chip memory map. -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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