linux-kernel - linux-next: manual merge of the pinctrl tree with the driver-core.current tree

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Date:	Mon, 24 Dec 2012 12:47:08 +1100
From:	Stephen Rothwell <sfr@...b.auug.org.au>
To:	Linus Walleij <linus.walleij@...aro.org>
Cc:	linux-next@...r.kernel.org, linux-kernel@...r.kernel.org,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Barry Song <Baohua.Song@....com>
Subject: linux-next: manual merge of the pinctrl tree with the
 driver-core.current tree

Hi Linus,

Today's linux-next merge of the pinctrl tree got a conflict in
drivers/pinctrl/pinctrl-sirf.c between commit c2c57b329c7b ("Drivers:
pinctrl: remove __dev* attributes") from the driver-core.current tree and
commit 19d601d8e0a7 ("pinctrl: sirf: enable GPIO pullup/down
configuration from dts") from the pinctrl tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

-- 
Cheers,
Stephen Rothwell                    sfr@...b.auug.org.au
http://www.canb.auug.org.au/~sfr/

diff --cc drivers/pinctrl/pinctrl-sirf.c
index c776046,30e1a38..0000000
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@@ -1663,7 -1663,45 +1663,45 @@@ const struct irq_domain_ops sirfsoc_gpi
  	.xlate = irq_domain_xlate_twocell,
  };
  
+ static void sirfsoc_gpio_set_pullup(const u32 *pullups)
+ {
+ 	int i, n;
+ 	const unsigned long *p = (const unsigned long *)pullups;
+ 
+ 	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
+ 		n = find_first_bit(p + i, BITS_PER_LONG);
+ 		while (n < BITS_PER_LONG) {
+ 			u32 offset = SIRFSOC_GPIO_CTRL(i, n);
+ 			u32 val = readl(sgpio_bank[i].chip.regs + offset);
+ 			val |= SIRFSOC_GPIO_CTL_PULL_MASK;
+ 			val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
+ 			writel(val, sgpio_bank[i].chip.regs + offset);
+ 
+ 			n = find_next_bit(p + i, BITS_PER_LONG, n + 1);
+ 		}
+ 	}
+ }
+ 
+ static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
+ {
+ 	int i, n;
+ 	const unsigned long *p = (const unsigned long *)pulldowns;
+ 
+ 	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
+ 		n = find_first_bit(p + i, BITS_PER_LONG);
+ 		while (n < BITS_PER_LONG) {
+ 			u32 offset = SIRFSOC_GPIO_CTRL(i, n);
+ 			u32 val = readl(sgpio_bank[i].chip.regs + offset);
+ 			val |= SIRFSOC_GPIO_CTL_PULL_MASK;
+ 			val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
+ 			writel(val, sgpio_bank[i].chip.regs + offset);
+ 
+ 			n = find_next_bit(p + i, BITS_PER_LONG, n + 1);
+ 		}
+ 	}
+ }
+ 
 -static int __devinit sirfsoc_gpio_probe(struct device_node *np)
 +static int sirfsoc_gpio_probe(struct device_node *np)
  {
  	int i, err = 0;
  	struct sirfsoc_gpio_bank *bank;

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