linux-kernel - Re: [PATCH v2 1/3] dmaengine: add dma_get_channel

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Message-ID: <20130120164153.GD21407@beef>
Date:	Sun, 20 Jan 2013 11:41:53 -0500
From:	Matt Porter <mporter@...com>
To:	Vinod Koul <vinod.koul@...el.com>
Cc:	Dan Williams <djbw@...com>, Chris Ball <cjb@...top.org>,
	Grant Likely <grant.likely@...retlab.ca>,
	Linux DaVinci Kernel List 
	<davinci-linux-open-source@...ux.davincidsp.com>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Linux MMC List <linux-mmc@...r.kernel.org>
Subject: Re: [PATCH v2 1/3] dmaengine: add dma_get_channel_caps()

On Sun, Jan 20, 2013 at 12:52:43PM +0000, Vinod Koul wrote:
> On Thu, Jan 10, 2013 at 02:07:04PM -0500, Matt Porter wrote:
> > +/* struct dmaengine_chan_caps - expose capability of a channel
> > + * Note: each channel can have same or different capabilities
> > + *
> > + * This primarily classifies capabilities into
> > + * a) APIs/ops supported
> > + * b) channel physical capabilities
> > + *
> > + * @cap_mask: api/ops capability (DMA_INTERRUPT and DMA_PRIVATE
> > + *	       are invalid api/ops and will never be set)
> > + * @seg_nr: maximum number of SG segments supported on a SG/SLAVE
> > + *	    channel (0 for no maximum or not a SG/SLAVE channel)
> > + * @seg_len: maximum length of SG segments supported on a SG/SLAVE
> > + *	     channel (0 for no maximum or not a SG/SLAVE channel)
> > + */
> > +struct dmaengine_chan_caps {
> > +	dma_cap_mask_t cap_mask;
> > +	int seg_nr;
> > +	int seg_len;
> > +};
> Now am really unclear why we would need direction as argument.

Best explanation is my reply to your comments on 0/3. In summary, the
direction allows the edma driver to select the src vs dst addr_width and
maxburst fields to be used to calculate the max segment size that can
be handled.

> Also, I would add the channel physical capablities like direction, widths,
> lengths etc supported.

Ok, I can take a stab at this...I didn't bother initially as I don't
have user for that info at this point. Though, I suppose we don't have
an immediate user for the cap_mask either.

> > +/**
> > + * dma_get_channel_caps - flush pending transactions to HW
> flush pending... ???

ugh, c&p fail...will fix.

> 
> > + * driver does not implement per channel capbilities then
> > + * NULL is returned.
> > + */
> > +static inline struct dmaengine_chan_caps
> > +*dma_get_channel_caps(struct dma_chan *chan, enum dma_transfer_direction dir)
> you need to add this for when CONFIG_DMA_ENGINE is not defined as well.

ok, will fix.

> > +{
> > +	if (chan->device->device_channel_caps)
> > +		return chan->device->device_channel_caps(chan, dir);
> > +	return NULL;
> > +}
> > +
> >  enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
> >  #ifdef CONFIG_DMA_ENGINE
> >  enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
> --
> ~Vinod
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