linux-kernel - Re: [RFC PATCH 1/5] x86: Add cpu capability flag X86_FEATURE_TSC_S3

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Message-ID: <20130121075900.GA509@feng-snb>
Date:	Mon, 21 Jan 2013 15:59:00 +0800
From:	Feng Tang <feng.tang@...el.com>
To:	Thomas Gleixner <tglx@...utronix.de>,
	John Stultz <john.stultz@...aro.org>,
	Ingo Molnar <mingo@...e.hu>,
	"H. Peter Anvin" <hpa@...ux.intel.com>, x86@...nel.org,
	Len Brown <lenb@...nel.org>,
	"Rafael J. Wysocki" <rafael.j.wysocki@...el.com>,
	linux-kernel@...r.kernel.org
Subject: Re: [RFC PATCH 1/5] x86: Add cpu capability flag
 X86_FEATURE_TSC_S3_NOTSTOP

On Mon, Jan 21, 2013 at 02:27:29AM -0500, Chen Gong wrote:
> On Mon, Jan 21, 2013 at 02:38:41PM +0800, Feng Tang wrote:
> > Date:	Mon, 21 Jan 2013 14:38:41 +0800
> > From: Feng Tang <feng.tang@...el.com>
> > To: Thomas Gleixner <tglx@...utronix.de>, John Stultz
> >  <john.stultz@...aro.org>, Ingo Molnar <mingo@...e.hu>, "H. Peter Anvin"
> >  <hpa@...ux.intel.com>, x86@...nel.org, Len Brown <lenb@...nel.org>,
> >  "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>,
> >  linux-kernel@...r.kernel.org
> > Cc: Feng Tang <feng.tang@...el.com>
> > Subject: [RFC PATCH 1/5] x86: Add cpu capability flag
> >  X86_FEATURE_TSC_S3_NOTSTOP
> > X-Mailer: git-send-email 1.7.9.5
> > 
> > On some new Intel Atom processors (Penwell and Cloverview), there is
> > a feature that the TSC won't stop S3, say the TSC value won't be
> > reset to 0 after resume. This feature makes TSC a more reliable
> > clocksource and could benefit the timekeeping code during system
> > suspend/resume cycle, so add a flag for it.
> > 
> > Signed-off-by: Feng Tang <feng.tang@...el.com>
> > ---
> >  arch/x86/include/asm/cpufeature.h |    1 +
> >  arch/x86/kernel/cpu/intel.c       |   12 ++++++++++++
> >  2 files changed, 13 insertions(+)
> > 
> > diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> > index 2d9075e..f7e1eac 100644
> > --- a/arch/x86/include/asm/cpufeature.h
> > +++ b/arch/x86/include/asm/cpufeature.h
> > @@ -100,6 +100,7 @@
> >  #define X86_FEATURE_AMD_DCM     (3*32+27) /* multi-node processor */
> >  #define X86_FEATURE_APERFMPERF	(3*32+28) /* APERFMPERF */
> >  #define X86_FEATURE_EAGER_FPU	(3*32+29) /* "eagerfpu" Non lazy FPU restore */
> > +#define X86_FEATURE_TSC_S3_NOTSTOP (3*32+30) /* TSC doesn't stop in S3 state */
> >  
> We have an existed "TSC always running in C3+" feature and name it as
> X86_FEATURE_NONSTOP_TSC, so how about naming it with the same style,
> like X86_FEATURE_NONSTOP_TSC_S3?

Yeah, actually I used a name X86_FEATURE_xxx_TSC, then I did a grep,
and found there is no unified name convention for TSC, so I chose such
a name.

--------------
#grep _TSC arch/x86/include/asm/cpufeature.h
#define X86_FEATURE_TSC         (0*32+ 4) /* Time Stamp Counter */
#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
#define X86_FEATURE_TSC_S3_NOTSTOP (3*32+30) /* TSC doesn't stop in S3 state */
#define X86_FEATURE_TSC_DEADLINE_TIMER  (4*32+24) /* Tsc deadline timer */
#define X86_FEATURE_TSCRATEMSR  (8*32+ 9) /* "tsc_scale" AMD TSC scaling support */
#define X86_FEATURE_TSC_ADJUST  (9*32+ 1) /* TSC adjustment MSR 0x3b */

Thanks,
Feng






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