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Message-ID: <CACRpkdZrmq8=_=BwvB9wZYxHEQZRZ1pVqD3+7B=YORU=rpnOOw@mail.gmail.com>
Date:	Wed, 23 Jan 2013 13:19:19 +0100
From:	Linus Walleij <linus.walleij@...aro.org>
To:	Fabio Baltieri <fabio.baltieri@...aro.org>
Cc:	Srinidhi Kasagar <srinidhi.kasagar@...ricsson.com>,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Maxime Coquelin <maxime.coquelin@...ricsson.com>
Subject: Re: [PATCH] ARM: mach-ux500: enable 128KB way L2 cache on DB8540

On Wed, Jan 23, 2013 at 11:27 AM, Fabio Baltieri
<fabio.baltieri@...aro.org> wrote:

> From: Maxime Coquelin <maxime.coquelin@...ricsson.com>
>
> DB8540 L2 was configured with 64KB way size, but it has 128KB as AP9540.
>
> Fix this by modifying ux500_l2x0_init() to use 128KB way size for all
> cpus in the x540 family.
>
> Signed-off-by: Maxime Coquelin <maxime.coquelin@...ricsson.com>
> Acked-by: Linus Walleij <linus.walleij@...aro.org>
> Signed-off-by: Fabio Baltieri <fabio.baltieri@...aro.org>

Applied to my ux500-core branch.

Yours,
Linus Walleij
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