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Message-ID: <20130131061248.GF2765@S2101-09.ap.freescale.net>
Date:	Thu, 31 Jan 2013 14:12:50 +0800
From:	Shawn Guo <shawn.guo@...aro.org>
To:	Anson Huang <b20788@...escale.com>
CC:	<devicetree-discuss@...ts.ozlabs.org>, <linux-doc@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <grant.likely@...retlab.ca>,
	<rob.herring@...xeda.com>, <rob@...dley.net>,
	<broonie@...nsource.wolfsonmicro.com>
Subject: Re: [PATCH V3] regulators: anatop: add set_voltage_time_sel interface

On Thu, Jan 31, 2013 at 11:23:53AM -0500, Anson Huang wrote:
> some of anatop's regulators(cpu, vddpu and vddsoc) have
> register settings about LDO's step time, which will impact
> the LDO ramp up speed, need to use set_voltage_time_sel
> interface to add necessary delay everytime LDOs' voltage
> is increased.
> 
> offset 0x170:
> bit [24-25]: cpu
> bit [26-27]: vddpu
> bit [28-29]: vddsoc
> 
> field definition:
> 0'b00: 64 cycles of 24M clock;
> 0'b01: 128 cycles of 24M clock;
> 0'b02: 256 cycles of 24M clock;
> 0'b03: 512 cycles of 24M clock;
> 
> Signed-off-by: Anson Huang <b20788@...escale.com>

Acked-by: Shawn Guo <shawn.guo@...aro.org>

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