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Message-ID: <CABPqkBQ_=BwGhgB3UQZ=4k2uYiATaTCNwybQpa9uKTNUJ3kvEg@mail.gmail.com>
Date: Fri, 1 Feb 2013 18:26:09 +0100
From: Stephane Eranian <eranian@...gle.com>
To: Andi Kleen <andi@...stfloor.org>
Cc: Ingo Molnar <mingo@...nel.org>,
LKML <linux-kernel@...r.kernel.org>,
Peter Zijlstra <a.p.zijlstra@...llo.nl>,
Andrew Morton <akpm@...ux-foundation.org>,
Arnaldo Carvalho de Melo <acme@...hat.com>,
Jiri Olsa <jolsa@...hat.com>,
Namhyung Kim <namhyung@...nel.org>,
Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH 03/12] perf, x86: Basic Haswell PEBS support v4
On Thu, Jan 31, 2013 at 11:51 PM, Andi Kleen <andi@...stfloor.org> wrote:
> From: Andi Kleen <ak@...ux.intel.com>
>
> Add basic PEBS support for Haswell.
> The constraints are similar to SandyBridge with a few new events.
>
> v2: Readd missing pebs_aliases
> v3: Readd missing hunk. Fix some constraints.
> v4: Fix typo in PEBS event table (Stephane Eranian)
> Signed-off-by: Andi Kleen <ak@...ux.intel.com>
Looks ok to me.
Reviewed-by: Stephane Eranian <eranian@...gle.com>
> ---
> arch/x86/kernel/cpu/perf_event.h | 2 ++
> arch/x86/kernel/cpu/perf_event_intel.c | 6 ++++--
> arch/x86/kernel/cpu/perf_event_intel_ds.c | 29 +++++++++++++++++++++++++++++
> 3 files changed, 35 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
> index 8941899..1567b0d 100644
> --- a/arch/x86/kernel/cpu/perf_event.h
> +++ b/arch/x86/kernel/cpu/perf_event.h
> @@ -596,6 +596,8 @@ extern struct event_constraint intel_snb_pebs_event_constraints[];
>
> extern struct event_constraint intel_ivb_pebs_event_constraints[];
>
> +extern struct event_constraint intel_hsw_pebs_event_constraints[];
> +
> struct event_constraint *intel_pebs_constraints(struct perf_event *event);
>
> void intel_pmu_pebs_enable(struct perf_event *event);
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index 78045e5..8163ebf 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -826,7 +826,8 @@ static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
> return true;
>
> /* implicit branch sampling to correct PEBS skid */
> - if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
> + if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 &&
> + x86_pmu.intel_cap.pebs_format < 2)
> return true;
>
> return false;
> @@ -2127,8 +2128,9 @@ __init int intel_pmu_init(void)
> intel_pmu_lbr_init_snb();
>
> x86_pmu.event_constraints = intel_hsw_event_constraints;
> -
> + x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
> x86_pmu.extra_regs = intel_snb_extra_regs;
> + x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
> /* all extra regs are per-cpu when HT is on */
> x86_pmu.er_flags |= ERF_HAS_RSP_1;
> x86_pmu.er_flags |= ERF_NO_HT_SHARING;
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> index 9d0dae0..0252930 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> @@ -427,6 +427,35 @@ struct event_constraint intel_ivb_pebs_event_constraints[] = {
> EVENT_CONSTRAINT_END
> };
>
> +struct event_constraint intel_hsw_pebs_event_constraints[] = {
> + INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
> + INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
> + INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
> + INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
> + INTEL_UEVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
> + INTEL_UEVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
> + INTEL_UEVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.NEAR_TAKEN */
> + INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.* */
> + INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
> + INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
> + INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
> + INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
> + INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
> + INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
> + INTEL_UEVENT_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
> + INTEL_UEVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */
> + INTEL_UEVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */
> + INTEL_UEVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L3_HIT */
> + INTEL_UEVENT_CONSTRAINT(0x40d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.HIT_LFB */
> + INTEL_UEVENT_CONSTRAINT(0x01d2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */
> + INTEL_UEVENT_CONSTRAINT(0x02d2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */
> + INTEL_UEVENT_CONSTRAINT(0x01d3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM */
> + INTEL_UEVENT_CONSTRAINT(0x04c8, 0xf), /* HLE_RETIRED.Abort */
> + INTEL_UEVENT_CONSTRAINT(0x04c9, 0xf), /* RTM_RETIRED.Abort */
> +
> + EVENT_CONSTRAINT_END
> +};
> +
> struct event_constraint *intel_pebs_constraints(struct perf_event *event)
> {
> struct event_constraint *c;
> --
> 1.7.7.6
>
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