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Message-ID: <20130206065340.416a708b@redhat.com>
Date: Wed, 6 Feb 2013 06:53:40 -0200
From: Mauro Carvalho Chehab <mchehab@...hat.com>
To: Yinghai Lu <yinghai@...nel.org>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>,
Jiang Liu <jiang.liu@...wei.com>,
Tony Luck <tony.luck@...el.com>,
"Rafael J. Wysocki" <rjw@...k.pl>,
Taku Izumi <izumi.taku@...fujitsu.com>,
Toshi Kani <toshi.kani@...com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-pci@...r.kernel.org, Russell King <linux@....linux.org.uk>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 00/22] PCI: Iterate pci host bridge instead of pci
root bus
Em Tue, 5 Feb 2013 16:47:10 -0800
Yinghai Lu <yinghai@...nel.org> escreveu:
> On Tue, Feb 5, 2013 at 4:19 PM, Bjorn Helgaas <bhelgaas@...gle.com> wrote:
> >
> > Maybe. I'd rather not introduce for_each_pci_host_bridge() at all, if
> > we can avoid it. Every place it's used is a place we have to audit to
> > make sure it's safe. I think your audit above is correct and
> > complete, but it relies on way too much architecture knowledge. It's
> > better if we can deduce correctness without knowing which arches
> > support hotplug and which CPUs support EDAC.
> >
> > As soon as for_each_pci_host_bridge() is in the tree, those uses can
> > be copied to even more places. It's a macro, so it's usable by any
> > module, even out-of-tree ones that we'll never see and can't fix. So
> > we won't really have a good way to deprecate and remove it.
>
> Now we only have two references in modules.
>
> drivers/edac/i7core_edac.c: for_each_pci_host_bridge(host_bridge) {
> drivers/pci/hotplug/sgi_hotplug.c: for_each_pci_host_bridge(host_bridge) {
>
> for the sgi_hotplug.c, it should be same problem that have for acpiphp
> and pciehp.
> need to make it support pci host bridge hotplug anyway.
>
> for edac, we need to check Mauro about their plan.
The i7core_pci_lastbus() code at i7core_edac is there to make it work
with some Nehalem/Nehalem-EP machines that hide the memory controller's
PCI ID by using an artificially low last bus. There's no plan to
support Nehalem-EX, as the information I got is that there's no way
to access the memory controller registers on it without interfering with
BIOS.
It should be noticed, however, that I got a report of a Sandy Bridge
server that is also hiding the memory controller's PCI address.
So, maybe we'll need to add later some logic at sb_edac to unhide the
memory controller, just like the one in i7core_edac.
>
> After those two are addressed, we can drop that EXPORT_SYMBOL_GPL for
> pci_get_next_host_bridge.
>
> We do have pci_get_domain_bus_and_slot() as export symbol.
> So we export pci_get_next_host_bridge should be ok now.
> and it would be better than export root buses list.
>
> Thanks
>
> Yinghai
--
Cheers,
Mauro
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