linux-kernel - Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

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Message-ID: <20130212151426.GA30577@one.firstfloor.org>
Date:	Tue, 12 Feb 2013 16:14:26 +0100
From:	Andi Kleen <andi@...stfloor.org>
To:	Ingo Molnar <mingo@...nel.org>
Cc:	Andi Kleen <andi@...stfloor.org>, linux-kernel@...r.kernel.org,
	eranian@...gle.com, Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

On Tue, Feb 12, 2013 at 09:43:46AM +0100, Ingo Molnar wrote:
> Was this stress-tested on all affected main CPU types, or only 
> on Haswell?

I tested it on Haswell and Ivy Bridge. I can also try
Westmere and a Saltwell(Atom), but for the majority of other family 6
systems I'll need to rely on the community.

White listing is somewhat difficult because it affects the architectural
mode too.

I don't really expect problems from this change, we should probably
have always done it like this.

-Andi

-- 
ak@...ux.intel.com -- Speaking for myself only.
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