>From mc74hc00@gmail.com Mon Jan 14 03:02:20 2013 Return-path: Envelope-to: wim@infomag.iguana.be Delivery-date: Mon, 14 Jan 2013 03:02:20 +0100 Received: from ylaen.iguana.be ([178.21.116.169]) by spo001.leaseweb.com with esmtp (Exim 4.50) id 1TuZNU-0006Zi-0P for wim@infomag.iguana.be; Mon, 14 Jan 2013 03:02:20 +0100 Received: from mail-pb0-f45.google.com (mail-pb0-f45.google.com [209.85.160.45]) by ylaen.iguana.be (Postfix) with ESMTP id 939FC174278 for ; Mon, 14 Jan 2013 03:02:19 +0100 (CET) Received: by mail-pb0-f45.google.com with SMTP id mc8so1875722pbc.32 for ; Sun, 13 Jan 2013 18:02:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=Al12X3CF48UZXAYSA0AbzpLWDndmh59rkg9CMqG3eKs=; b=BN3M1HJsUrmYnOe3KiT2w9jZTOWHevYNdIbLumjQWul8MbPVI1WDie98dgoG21C18P BuaHoo82fmCZBViD0qyuQz0RI0vySln5olsfpBsCKJVWTFDSAAg/kysHmcqOVp6sWpDI VPSe22vIVgxiNtqK0BdwGLjyvhQJ7Cgnv/3CrIa4h1HUfP8hKMwy/9V6SCe4VRpt7bOZ ZqTxpMfQ95pesNTKJuZEx2vqL5LM2WMVqUhneVR1dG4ceFTbOZ3xF57waoUEszGFlrmq 0owzHTSi1BVF1wlxEfYXPuSie/gS2Yl9AGqHoaXm3DN3aSXwXbqnIK5VdUi/3Cir7CUK zj3Q== X-Received: by 10.66.83.165 with SMTP id r5mr229452746pay.3.1358128938114; Sun, 13 Jan 2013 18:02:18 -0800 (PST) Received: from localhost (p7204-ipngn2902marunouchi.tokyo.ocn.ne.jp. [180.47.244.204]) by mx.google.com with ESMTPS id qh4sm7226051pbb.9.2013.01.13.18.02.14 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 13 Jan 2013 18:02:16 -0800 (PST) From: Takahisa Tanaka To: linux-watchdog@vger.kernel.org Cc: Wim Van Sebroeck , Paul Menzel , Arkadiusz Miskiewicz , Bjorn Helgaas , Andrew Morton , Jonathan Nieder , linux-kernel@vger.kernel.org, Florian Mickler , Takahisa Tanaka Subject: [PATCH 1/2] watchdog: sp5100_tco: Fix wrong indirect I/O access for getting value of reserved bits Date: Mon, 14 Jan 2013 11:01:57 +0900 Message-Id: <1358128918-4415-1-git-send-email-mc74hc00@gmail.com> X-Mailer: git-send-email 1.7.11.7 Content-Length: 1656 Lines: 42 In case of SB800 or later chipset and re-programming MMIO address(*), sp5100_tco module may read incorrect value of reserved bit, because the module reads a value from an incorrect I/O address. However, this bug doesn't cause a problem, because when re-programming MMIO address, by chance the module writes zero (this is BIOS's default value) to the low three bits of register. * In most cases, PC with SB8x0 or later chipset doesn't need to re-programming MMIO address, because such PC can enable AcpiMmio and can use 0xfed80b00 for watchdog register base address. This patch fixes this bug. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176 Signed-off-by: Takahisa Tanaka Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/sp5100_tco.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/sp5100_tco.c b/drivers/watchdog/sp5100_tco.c index 2b0e000..5dfe86e 100644 --- a/drivers/watchdog/sp5100_tco.c +++ b/drivers/watchdog/sp5100_tco.c @@ -500,14 +500,15 @@ static unsigned char sp5100_tco_setupdevice(void) /* Restore to the low three bits, if chipset is SB8x0(or later) */ if (sp5100_tco_pci->revision >= 0x40) { u8 reserved_bit; - reserved_bit = inb(base_addr) & 0x7; + outb(base_addr+0, index_reg); + reserved_bit = inb(data_reg) & 0x7; val |= (u32)reserved_bit; } /* Re-programming the watchdog timer base address */ outb(base_addr+0, index_reg); /* Low three bits of BASE are reserved */ - outb((val >> 0) & 0xf8, data_reg); + outb((val >> 0) & 0xff, data_reg); outb(base_addr+1, index_reg); outb((val >> 8) & 0xff, data_reg); outb(base_addr+2, index_reg); -- 1.7.11.7