linux-kernel - Re: [PATCH 5/5] arm: dts: Convert mvebu device tree files to 64 bits

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Date:	Thu, 21 Mar 2013 16:30:26 -0400
From:	Jason Cooper <jason@...edaemon.net>
To:	Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
Cc:	Andrew Lunn <andrew@...n.ch>, Lior Amsalem <alior@...vell.com>,
	Ike Pan <ike.pan@...onical.com>,
	Nadav Haklai <nadavh@...vell.com>,
	David Marlin <dmarlin@...hat.com>,
	Yehuda Yitschak <yehuday@...vell.com>,
	Tawfik Bayouk <tawfik@...vell.com>,
	Dan Frazier <dann.frazier@...onical.com>,
	Eran Ben-Avi <benavi@...vell.com>,
	Ezequiel Garcia <ezequiel.garcia@...e-electrons.com>,
	Leif Lindholm <leif.lindholm@....com>,
	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
	Arnd Bergmann <arnd@...db.de>, Jon Masters <jcm@...hat.com>,
	devicetree-discuss@...ts.ozlabs.org,
	Rob Herring <rob.herring@...xeda.com>,
	Gregory CLEMENT <gregory.clement@...e-electrons.com>,
	linux-arm-kernel@...ts.infradead.org,
	Chris Van Hoof <vanhoof@...onical.com>,
	Nicolas Pitre <nico@...xnic.net>, linux-kernel@...r.kernel.org,
	Grant Likely <grant.likely@...retlab.ca>,
	Maen Suleiman <maen@...vell.com>,
	Shadi Ammouri <shadi@...vell.com>,
	Olof Johansson <olof@...om.net>
Subject: Re: [PATCH 5/5] arm: dts: Convert mvebu device tree files to 64
 bits

On Thu, Mar 21, 2013 at 09:22:36PM +0100, Thomas Petazzoni wrote:
> Dear Andrew Lunn,
> 
> On Thu, 21 Mar 2013 21:15:33 +0100, Andrew Lunn wrote:
> 
> > Could you recommend a document which introduces LPAE.
> > 
> > Only being able to address 7GB seems a bit odd to me. I kind of
> > expected you set up the translation tables to map a page in the 32 bit
> > address range to any arbitrary page in the 40 bit address range. So
> > leaving 0xC0000000 to 0xffffffff in the 32bit address range clear is
> > easy. But why do you loose space in the 40bit address range?
> 
> translation tables convert virtual addresses to physical addresses.
> Here, we are only talking about physical addresses. There is an overlap
> between the physical addresses used by the RAM, and the physical
> addresses at which I/O devices are visible.
> 
> And I'm not sure the SDRAM address decoding windows allows to split the
> first 4 GB of RAM into two areas, one that would be mapped starting at
> physical address 0x0, and another area that would be mapped at a
> different address (above 4 GB).
> 
> However, I'm unsure why 0xC0000000 was chosen. Why not 0xD0000000,
> where the internal registers currently start?

I had the same question earlier but got distracted by other things.
Thanks for bringing it up.  Gregory, shouldn't this be 0xD0000000?

thx,

Jason.
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