linux-kernel - Re: [RFC 0/2] PCI: Introduce MSI chip infrastructure

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20130325091534.GA21054@avionic-0098.mockup.avionic-design.de>
Date:	Mon, 25 Mar 2013 10:15:34 +0100
From:	Thierry Reding <thierry.reding@...onic-design.de>
To:	Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
Cc:	Andrew Murray <andrew.murray@....com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Arnd Bergmann <arnd@...db.de>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [RFC 0/2] PCI: Introduce MSI chip infrastructure

On Mon, Mar 25, 2013 at 09:38:47AM +0100, Thomas Petazzoni wrote:
> Dear Thierry Reding,
> 
> Thanks for your feedback!
> 
> On Mon, 25 Mar 2013 08:58:10 +0100, Thierry Reding wrote:
> 
> > That sounds very much like one of the use-cases that were discussed. The
> > easiest solution would probably be to add an API to look up an MSI chip
> > from a DT phandle, so that the PCIe controller's device node could have
> > it as a property, somewhat like this:
> > 
> > 	msi: interrupt-controller {
> > 	};
> > 
> > 	pcie-controller {
> > 		...
> > 		marvell,msi = <&msi>;
> > 		...
> > 	};
> 
> I'm not sure how to handle this msi interrupt controller with the main
> interrupt controller. For now, I have:
> 
>         mpic: interrupt-controller@...20000 {
>               reg = <0xd0020a00 0x2d0>,
>                     <0xd0021070 0x58>;
>         };
> 
> 	[...]
> 
> 	soc {
>                 interrupt-parent = <&mpic>;
> 		[...]
> 	};
> 
> And the MSI interrupt controller shares the same registers as the MPIC.
> So should it be something like:
> 
> 	interrupt-controller {
> 		reg = <0xd0020a00 0x2d0>,
>                     <0xd0021070 0x58>;
> 
> 		mpic {
> 			/* Not sure what to have here */
> 		};
> 
> 		msi {
> 
> 			/* Here either */
> 		};
> 	};
> 
> 	soc {
>                 interrupt-parent = <&mpic>;
> 
> 		pcie-controller {
> 			marvell,msi = <&msi>;
> 		};
> 	};
> 
> Or some other idea?

I think you can just make this:

	mpic: interrupt-controller@...20000 {
		...
	};

	...

	soc {
		pcie-controller {
			marvell,msi = <&mpic>;
		};
	};

And everything else should just work given the APIs I mentioned. But as
you said it'd be good if somebody else could share their opinion about
this.

Thierry

Content of type "application/pgp-signature" skipped