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Message-ID: <20130326092306.GA8553@the-dreams.de>
Date: Tue, 26 Mar 2013 10:23:07 +0100
From: Wolfram Sang <wsa@...-dreams.de>
To: Yuvaraj CD <yuvaraj.lkml@...il.com>
Cc: Naveen Krishna Chatradhi <ch.naveen@...sung.com>,
linux-i2c@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-samsung-soc@...r.kernel.org, w.sang@...gutronix.de,
khali@...ux-fr.org, ben-linux@...ff.org, grant.likely@...retlab.ca,
devicetree-discuss@...ts.ozlabs.org, sjg@...omium.org,
grundler@...omium.org, naveenkrishna.ch@...il.com,
broonie@...nsource.wolfsonmicro.com
Subject: Re: [RFC: PATCH v5] i2c: exynos5: add High Speed I2C controller
driver
> > + /* CLK_DIV max is 256 */
> > + for (i = 0; i < 256; i++) {
> > + utemp1 = utemp0 / (i + 1);
> > + /* SCLK_L/H max is 256 / 2 */
> > + if (utemp1 < 128) {
> I think TSCLK_L and TSCLK_H both can be configured upto 255.Why
> limiting it to < 128 ?
> By limiting it to < 128 dont we achieve lesser SCL clock?
Thanks for reviewing but please quote only the relevant part of the
message (like I did). This improves readability a lot.
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